select DMA_NONCOHERENT
        select HW_HAS_PCI
        select IRQ_CPU
-       select SYS_HAS_CPU_MIPS32_R1
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_LITTLE_ENDIAN
-       select SSB
-       select SSB_DRIVER_MIPS
-       select SSB_DRIVER_EXTIF
-       select SSB_EMBEDDED
-       select SSB_B43_PCI_BRIDGE if PCI
-       select SSB_PCICORE_HOSTMODE if PCI
        select GENERIC_GPIO
        select SYS_HAS_EARLY_PRINTK
        select CFE
 
 source "arch/mips/alchemy/Kconfig"
 source "arch/mips/ath79/Kconfig"
+source "arch/mips/bcm47xx/Kconfig"
 source "arch/mips/bcm63xx/Kconfig"
 source "arch/mips/jazz/Kconfig"
 source "arch/mips/jz4740/Kconfig"
 
--- /dev/null
+if BCM47XX
+
+config BCM47XX_SSB
+       bool "SSB Support for Broadcom BCM47XX"
+       select SYS_HAS_CPU_MIPS32_R1
+       select SSB
+       select SSB_DRIVER_MIPS
+       select SSB_DRIVER_EXTIF
+       select SSB_EMBEDDED
+       select SSB_B43_PCI_BRIDGE if PCI
+       select SSB_PCICORE_HOSTMODE if PCI
+       default y
+       help
+        Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support.
+
+        This will generate an image with support for SSB and MIPS32 R1 instruction set.
+
+endif
 
 # under Linux.
 #
 
-obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o
+obj-y                          += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o
+obj-$(CONFIG_BCM47XX_SSB)      += wgt634u.o
 
 int gpio_request(unsigned gpio, const char *tag)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) &&
                    ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
                        return -EBUSY;
 
                return 0;
+#endif
        }
        return -EINVAL;
 }
 void gpio_free(unsigned gpio)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) &&
                    ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
 
                clear_bit(gpio, gpio_in_use);
                return;
+#endif
        }
 }
 EXPORT_SYMBOL(gpio_free);
 int gpio_to_irq(unsigned gpio)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco))
                        return ssb_mips_irq(bcm47xx_bus.ssb.chipco.dev) + 2;
                        return ssb_mips_irq(bcm47xx_bus.ssb.extif.dev) + 2;
                else
                        return -EINVAL;
+#endif
        }
        return -EINVAL;
 }
 
 /* Probe for NVRAM header */
 static void early_nvram_init(void)
 {
+#ifdef CONFIG_BCM47XX_SSB
        struct ssb_mipscore *mcore_ssb;
+#endif
        struct nvram_header *header;
        int i;
        u32 base = 0;
        u32 *src, *dst;
 
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                mcore_ssb = &bcm47xx_bus.ssb.mipscore;
                base = mcore_ssb->flash_window;
                lim = mcore_ssb->flash_window_size;
                break;
+#endif
        }
 
        off = FLASH_MIN;
 
        },
 };
 
+#ifdef CONFIG_BCM47XX_SSB
 static int __init uart8250_init_ssb(void)
 {
        int i;
        }
        return platform_device_register(&uart8250_device);
 }
+#endif
 
 static int __init uart8250_init(void)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                return uart8250_init_ssb();
+#endif
        }
        return -EINVAL;
 }
 
        local_irq_disable();
        /* Set the watchdog timer to reset immediately */
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1);
                break;
+#endif
        }
        while (1)
                cpu_relax();
        /* Disable interrupts and watchdog and spin forever */
        local_irq_disable();
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0);
                break;
+#endif
        }
        while (1)
                cpu_relax();
 }
 
+#ifdef CONFIG_BCM47XX_SSB
 #define READ_FROM_NVRAM(_outvar, name, buf) \
        if (nvram_getprefix(prefix, name, buf, sizeof(buf)) >= 0)\
                sprom->_outvar = simple_strtoul(buf, NULL, 0);
                }
        }
 }
+#endif
 
 void __init plat_mem_setup(void)
 {
        struct cpuinfo_mips *c = ¤t_cpu_data;
 
+#ifdef CONFIG_BCM47XX_SSB
        bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB;
        bcm47xx_register_ssb();
+#endif
 
        _machine_restart = bcm47xx_machine_restart;
        _machine_halt = bcm47xx_machine_halt;
 
        write_c0_compare(0xffff);
 
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
                break;
+#endif
        }
 
        if (!hz)
 
 #include <linux/ssb/ssb.h>
 
 enum bcm47xx_bus_type {
+#ifdef CONFIG_BCM47XX_SSB
        BCM47XX_BUS_TYPE_SSB,
+#endif
 };
 
 union bcm47xx_bus {
+#ifdef CONFIG_BCM47XX_SSB
        struct ssb_bus ssb;
+#endif
 };
 
 extern union bcm47xx_bus bcm47xx_bus;
 
 static inline int gpio_get_value(unsigned gpio)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                return ssb_gpio_in(&bcm47xx_bus.ssb, 1 << gpio);
+#endif
        }
        return -EINVAL;
 }
 static inline void gpio_set_value(unsigned gpio, int value)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio,
                             value ? 1 << gpio : 0);
+#endif
        }
 }
 
 static inline int gpio_direction_input(unsigned gpio)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 0);
                return 0;
+#endif
        }
        return -EINVAL;
 }
 static inline int gpio_direction_output(unsigned gpio, int value)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                /* first set the gpio out value */
                ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio,
                /* then set the gpio mode */
                ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 1 << gpio);
                return 0;
+#endif
        }
        return -EINVAL;
 }
 static inline int gpio_intmask(unsigned gpio, int value)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                ssb_gpio_intmask(&bcm47xx_bus.ssb, 1 << gpio,
                                 value ? 1 << gpio : 0);
                return 0;
+#endif
        }
        return -EINVAL;
 }
 static inline int gpio_polarity(unsigned gpio, int value)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << gpio,
                                  value ? 1 << gpio : 0);
                return 0;
+#endif
        }
        return -EINVAL;
 }
 
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/ssb/ssb.h>
+#include <bcm47xx.h>
 
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
 
 int pcibios_plat_dev_init(struct pci_dev *dev)
 {
+#ifdef CONFIG_BCM47XX_SSB
        int res;
        u8 slot, pin;
 
+       if (bcm47xx_bus_type !=  BCM47XX_BUS_TYPE_SSB)
+               return 0;
+
        res = ssb_pcibios_plat_dev_init(dev);
        if (res < 0) {
                printk(KERN_ALERT "PCI: Failed to init device %s\n",
        }
 
        dev->irq = res;
+#endif
        return 0;
 }
 
 {
        /* this is 2,5s on 100Mhz clock  and 2s on 133 Mhz */
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0xfffffff);
                break;
+#endif
        }
 }
 
 static inline int bcm47xx_wdt_hw_stop(void)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                return ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0);
+#endif
        }
        return -EINVAL;
 }