ASoC: fsl_spdif: Add support for i.MX8ULP

On i.MX8ULP the spdif works with EDMA, so add compatible
string and soc specific data for i.MX8ULP.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1631238562-27081-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
index 1c53719bb61e234d5456ec4cc7d9be234bd86403..928b59069283d487a8406a6e01972cc461d0cf3f 100644 (file)
--- a/sound/soc/fsl/fsl_spdif.c
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -186,6 +186,16 @@ static struct fsl_spdif_soc_data fsl_spdif_imx8mm = {
        .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
 };
 
+static struct fsl_spdif_soc_data fsl_spdif_imx8ulp = {
+       .imx = true,
+       .shared_root_clock = true,
+       .raw_capture_mode = false,
+       .interrupts = 1,
+       .tx_burst = 2,          /* Applied for EDMA */
+       .rx_burst = 2,          /* Applied for EDMA */
+       .tx_formats = SNDRV_PCM_FMTBIT_S24_LE,  /* Applied for EDMA */
+};
+
 /* Check if clk is a root clock that does not share clock source with others */
 static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk)
 {
@@ -1560,6 +1570,7 @@ static const struct of_device_id fsl_spdif_dt_ids[] = {
        { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, },
        { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, },
        { .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, },
+       { .compatible = "fsl,imx8ulp-spdif", .data = &fsl_spdif_imx8ulp, },
        {}
 };
 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);