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          Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
  
- config ARCH_SHMOBILE_LEGACY
-       bool "Renesas ARM SoCs (non-multiplatform)"
-       select ARCH_SHMOBILE
-       select ARM_PATCH_PHYS_VIRT if MMU
-       select CLKDEV_LOOKUP
-       select CPU_V7
-       select GENERIC_CLOCKEVENTS
-       select HAVE_ARM_SCU if SMP
-       select HAVE_ARM_TWD if SMP
-       select HAVE_SMP
-       select MIGHT_HAVE_CACHE_L2X0
-       select MULTI_IRQ_HANDLER
-       select NO_IOPORT_MAP
-       select PINCTRL
-       select PM_GENERIC_DOMAINS if PM
-       select SH_CLK_CPG
-       select SPARSE_IRQ
-       help
-         Support for Renesas ARM SoC platforms using a non-multiplatform
-         kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
-         and RZ families.
- 
  config ARCH_RPC
        bool "RiscPC"
 +      depends on MMU
        select ARCH_ACORN
        select ARCH_MAY_HAVE_PC_FDC
        select ARCH_SPARSEMEM_ENABLE
 
                        clocksource_gpt.name, clksrc.rate);
  }
  
- #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
+ static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
+               const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
+               const char *clksrc_prop, bool gptimer)
+ {
+       omap_clk_init();
+       omap_dmtimer_init();
+       omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
+ 
+       /* Enable the use of clocksource="gp_timer" kernel parameter */
+       if (use_gptimer_clksrc || gptimer)
+               omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
+                                               clksrc_prop);
+       else
+               omap2_sync32k_clocksource_init();
+ }
+ 
+ void __init omap_init_time(void)
+ {
+       __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
+                       2, "timer_sys_ck", NULL, false);
+ 
+       if (of_have_populated_dt())
 -              clocksource_of_init();
++              clocksource_probe();
+ }
+ 
+ #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
+ void __init omap3_secure_sync32k_timer_init(void)
+ {
+       __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
+                       2, "timer_sys_ck", NULL, false);
+ }
+ #endif /* CONFIG_ARCH_OMAP3 */
+ 
+ #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
+ void __init omap3_gptimer_timer_init(void)
+ {
+       __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
+                       1, "timer_sys_ck", "ti,timer-alwon", true);
+ }
+ #endif
+ 
+ #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) ||                \
+       defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
+ static void __init omap4_sync32k_timer_init(void)
+ {
+       __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
+                       2, "sys_clkin_ck", NULL, false);
+ }
+ 
+ void __init omap4_local_timer_init(void)
+ {
+       omap4_sync32k_timer_init();
 -      clocksource_of_init();
++      clocksource_probe();
+ }
+ #endif
+ 
+ #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
+ 
  /*
   * The realtime counter also called master counter, is a free-running
   * counter, which is related to real time. It produces the count used