drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+

BSpec does not show these WAs as applicable to GLK, and for CNL it
only shows them applicable for a super early pre-production stepping
we shouldn't be caring about anymore. Remove these so we can avoid
them on ICL too.

v2: Change how we check for gen9 display platforms (Ville).

Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181114012432.21809-1-paulo.r.zanoni@intel.com

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b11fac679e101f0f697b369967b4b46877abec8c..2a6ffb8b975a73b299635c672f16f8b15dc0d6a2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4730,28 +4730,31 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
        res_lines = div_round_up_fixed16(selected_result,
                                         wp->plane_blocks_per_line);
 
-       /* Display WA #1125: skl,bxt,kbl,glk */
-       if (level == 0 && wp->rc_surface)
-               res_blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
-
-       /* Display WA #1126: skl,bxt,kbl,glk */
-       if (level >= 1 && level <= 7) {
-               if (wp->y_tiled) {
-                       res_blocks += fixed16_to_u32_round_up(
-                                                       wp->y_tile_minimum);
-                       res_lines += wp->y_min_scanlines;
-               } else {
-                       res_blocks++;
-               }
+       if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
+               /* Display WA #1125: skl,bxt,kbl */
+               if (level == 0 && wp->rc_surface)
+                       res_blocks +=
+                               fixed16_to_u32_round_up(wp->y_tile_minimum);
+
+               /* Display WA #1126: skl,bxt,kbl */
+               if (level >= 1 && level <= 7) {
+                       if (wp->y_tiled) {
+                               res_blocks +=
+                                   fixed16_to_u32_round_up(wp->y_tile_minimum);
+                               res_lines += wp->y_min_scanlines;
+                       } else {
+                               res_blocks++;
+                       }
 
-               /*
-                * Make sure result blocks for higher latency levels are atleast
-                * as high as level below the current level.
-                * Assumption in DDB algorithm optimization for special cases.
-                * Also covers Display WA #1125 for RC.
-                */
-               if (result_prev->plane_res_b > res_blocks)
-                       res_blocks = result_prev->plane_res_b;
+                       /*
+                        * Make sure result blocks for higher latency levels are
+                        * atleast as high as level below the current level.
+                        * Assumption in DDB algorithm optimization for special
+                        * cases. Also covers Display WA #1125 for RC.
+                        */
+                       if (result_prev->plane_res_b > res_blocks)
+                               res_blocks = result_prev->plane_res_b;
+               }
        }
 
        /* The number of lines are ignored for the level 0 watermark. */