#size-cells = <1>;
                ranges = <0x0 0x0 0x43000000 0x20000>;
 
+               chipid@14 {
+                       compatible = "ti,am654-chipid";
+                       reg = <0x00000014 0x4>;
+               };
+
                serdes_ln_ctrl: mux-controller {
                        compatible = "mmio-mux";
                        #mux-control-cells = <1>;
                        mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
                };
+
+               phy_gmii_sel: phy@4044 {
+                       compatible = "ti,am654-phy-gmii-sel";
+                       reg = <0x4044 0x8>;
+                       #phy-cells = <1>;
+               };
+
+               epwm_tbclk: clock@4140 {
+                       compatible = "ti,am64-epwm-tbclk";
+                       reg = <0x4130 0x4>;
+                       #clock-cells = <1>;
+               };
        };
 
        gic500: interrupt-controller@1800000 {
                pinctrl-single,function-mask = <0xffffffff>;
        };
 
-       main_conf: syscon@43000000 {
-               compatible = "syscon", "simple-mfd";
-               reg = <0x00 0x43000000 0x00 0x20000>;
-               #address-cells = <1>;
-               #size-cells = <1>;
-               ranges = <0x00 0x00 0x43000000 0x20000>;
-
-               chipid@14 {
-                       compatible = "ti,am654-chipid";
-                       reg = <0x00000014 0x4>;
-               };
-
-               phy_gmii_sel: phy@4044 {
-                       compatible = "ti,am654-phy-gmii-sel";
-                       reg = <0x4044 0x8>;
-                       #phy-cells = <1>;
-               };
-
-               epwm_tbclk: clock@4140 {
-                       compatible = "ti,am64-epwm-tbclk";
-                       reg = <0x4130 0x4>;
-                       #clock-cells = <1>;
-               };
-       };
-
        main_timer0: timer@2400000 {
                compatible = "ti,am654-timer";
                reg = <0x00 0x2400000 0x00 0x400>;