return 0;
 }
 
+static int meson8b_devm_clk_prepare_enable(struct meson8b_dwmac *dwmac,
+                                          struct clk *clk)
+{
+       int ret;
+
+       ret = clk_prepare_enable(clk);
+       if (ret)
+               return ret;
+
+       devm_add_action_or_reset(dwmac->dev,
+                                (void(*)(void *))clk_disable_unprepare,
+                                dwmac->rgmii_tx_clk);
+
+       return 0;
+}
+
 static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
 {
        int ret;
                        return ret;
                }
 
-               ret = clk_prepare_enable(dwmac->rgmii_tx_clk);
+               ret = meson8b_devm_clk_prepare_enable(dwmac,
+                                                     dwmac->rgmii_tx_clk);
                if (ret) {
                        dev_err(dwmac->dev,
                                "failed to enable the RGMII TX clock\n");
                        return ret;
                }
-
-               devm_add_action_or_reset(dwmac->dev,
-                                       (void(*)(void *))clk_disable_unprepare,
-                                       dwmac->rgmii_tx_clk);
                break;
 
        case PHY_INTERFACE_MODE_RMII: