return wl->ops->boot(wl);
 }
 
+static void wl18xx_get_mac(struct wl1271 *wl)
+{
+       u32 mac1, mac2;
+
+       wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
+
+       mac1 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1);
+       mac2 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2);
+
+       /* these are the two parts of the BD_ADDR */
+       wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
+               ((mac1 & 0xff000000) >> 24);
+       wl->fuse_nic_addr = (mac1 & 0xffffff);
+
+       wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
+}
+
 static struct wlcore_ops wl18xx_ops = {
        .identify_chip  = wl18xx_identify_chip,
        .boot           = wl18xx_boot,
        .set_rx_csum = wl18xx_set_rx_csum,
        .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
        .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
+       .get_mac        = wl18xx_get_mac,
 };
 
 /* HT cap appropriate for wide channels */
 
 #define WL18XX_PG_VER_MASK             0x70
 #define WL18XX_PG_VER_OFFSET           4
 
+#define WL18XX_REG_FUSE_BD_ADDR_1      0xA02602
+#define WL18XX_REG_FUSE_BD_ADDR_2      0xA02606
+
 #define WL18XX_CMD_MBOX_ADDRESS                0xB007B4
 
 #define WL18XX_FW_STATUS_ADDR          0x50F8