#define __NVKM_MXM_H__
 #include <core/subdev.h>
 
-#define MXM_SANITISE_DCB 0x00000001
-
-struct nvkm_mxm {
-       struct nvkm_subdev subdev;
-       u32 action;
-       u8 *mxms;
-};
-
-static inline struct nvkm_mxm *
-nvkm_mxm(void *obj)
-{
-       return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MXM);
-}
-
-#define nvkm_mxm_create(p,e,o,d)                                            \
-       nvkm_mxm_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nvkm_mxm_init(p)                                                    \
-       nvkm_subdev_init_old(&(p)->subdev)
-#define nvkm_mxm_fini(p,s)                                                  \
-       nvkm_subdev_fini_old(&(p)->subdev, (s))
-int  nvkm_mxm_create_(struct nvkm_object *, struct nvkm_object *,
-                        struct nvkm_oclass *, int, void **);
-void nvkm_mxm_destroy(struct nvkm_mxm *);
-
-#define _nvkm_mxm_dtor _nvkm_subdev_dtor
-#define _nvkm_mxm_init _nvkm_subdev_init
-#define _nvkm_mxm_fini _nvkm_subdev_fini
-
-extern struct nvkm_oclass nv50_mxm_oclass;
+int nv50_mxm_new(struct nvkm_device *, int, struct nvkm_subdev **);
 #endif
 
        .imem = nv50_instmem_new,
        .mc = nv50_mc_new,
        .mmu = nv50_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .therm = nv50_therm_new,
 //     .timer = nv04_timer_new,
 //     .volt = nv40_volt_new,
        .imem = nv50_instmem_new,
        .mc = nv50_mc_new,
        .mmu = nv50_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .therm = g84_therm_new,
 //     .timer = nv04_timer_new,
 //     .volt = nv40_volt_new,
        .imem = nv50_instmem_new,
        .mc = nv50_mc_new,
        .mmu = nv50_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .therm = g84_therm_new,
 //     .timer = nv04_timer_new,
 //     .volt = nv40_volt_new,
        .imem = nv50_instmem_new,
        .mc = nv50_mc_new,
        .mmu = nv50_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .therm = g84_therm_new,
 //     .timer = nv04_timer_new,
 //     .volt = nv40_volt_new,
        .imem = nv50_instmem_new,
        .mc = g94_mc_new,
        .mmu = nv50_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .therm = g84_therm_new,
 //     .timer = nv04_timer_new,
 //     .volt = nv40_volt_new,
        .fuse = nv50_fuse_new,
        .clk = g84_clk_new,
 //     .therm = g84_therm_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
        .devinit = g84_devinit_new,
        .mc = g94_mc_new,
        .bus = g94_bus_new,
        .fuse = nv50_fuse_new,
        .clk = g84_clk_new,
 //     .therm = g84_therm_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
        .devinit = g98_devinit_new,
        .mc = g98_mc_new,
        .bus = g94_bus_new,
        .imem = nv50_instmem_new,
        .mc = g98_mc_new,
        .mmu = nv50_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .therm = g84_therm_new,
 //     .timer = nv04_timer_new,
 //     .volt = nv40_volt_new,
        .imem = nv50_instmem_new,
        .mc = g98_mc_new,
        .mmu = nv50_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gt215_pmu_new,
 //     .therm = gt215_therm_new,
 //     .timer = nv04_timer_new,
        .imem = nv50_instmem_new,
        .mc = g98_mc_new,
        .mmu = nv50_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gt215_pmu_new,
 //     .therm = gt215_therm_new,
 //     .timer = nv04_timer_new,
        .imem = nv50_instmem_new,
        .mc = g98_mc_new,
        .mmu = nv50_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gt215_pmu_new,
 //     .therm = gt215_therm_new,
 //     .timer = nv04_timer_new,
        .imem = nv50_instmem_new,
        .mc = g98_mc_new,
        .mmu = nv50_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .therm = g84_therm_new,
 //     .timer = nv04_timer_new,
 //     .volt = nv40_volt_new,
        .imem = nv50_instmem_new,
        .mc = g98_mc_new,
        .mmu = nv50_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .therm = g84_therm_new,
 //     .timer = nv04_timer_new,
 //     .volt = nv40_volt_new,
        .imem = nv50_instmem_new,
        .mc = g98_mc_new,
        .mmu = nv50_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gt215_pmu_new,
 //     .therm = gt215_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gf100_ltc_new,
        .mc = gf100_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gf100_pmu_new,
 //     .therm = gt215_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gf100_ltc_new,
        .mc = gf106_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gf100_pmu_new,
 //     .therm = gt215_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gf100_ltc_new,
        .mc = gf106_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gf100_pmu_new,
 //     .therm = gt215_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gf100_ltc_new,
        .mc = gf100_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gf100_pmu_new,
 //     .therm = gt215_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gf100_ltc_new,
        .mc = gf100_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gf100_pmu_new,
 //     .therm = gt215_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gf100_ltc_new,
        .mc = gf100_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gf100_pmu_new,
 //     .therm = gt215_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gf100_ltc_new,
        .mc = gf106_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gf100_pmu_new,
 //     .therm = gt215_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gf100_ltc_new,
        .mc = gf106_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .therm = gf110_therm_new,
 //     .timer = nv04_timer_new,
 //     .ce[0] = gf100_ce0_new,
        .ltc = gf100_ltc_new,
        .mc = gf106_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gf110_pmu_new,
 //     .therm = gf110_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gk104_ltc_new,
        .mc = gf106_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gk104_pmu_new,
 //     .therm = gf110_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gk104_ltc_new,
        .mc = gf106_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gk104_pmu_new,
 //     .therm = gf110_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gk104_ltc_new,
        .mc = gf106_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gf110_pmu_new,
 //     .therm = gf110_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gk104_ltc_new,
        .mc = gf106_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gk110_pmu_new,
 //     .therm = gf110_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gk104_ltc_new,
        .mc = gf106_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gk110_pmu_new,
 //     .therm = gf110_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gk104_ltc_new,
        .mc = gk20a_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gk208_pmu_new,
 //     .therm = gf110_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gk104_ltc_new,
        .mc = gk20a_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gk208_pmu_new,
 //     .therm = gf110_therm_new,
 //     .timer = nv04_timer_new,
        .ltc = gm107_ltc_new,
        .mc = gk20a_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gk208_pmu_new,
 //     .therm = gm107_therm_new,
 //     .timer = gk20a_timer_new,
        .ltc = gm107_ltc_new,
        .mc = gk20a_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gk208_pmu_new,
 //     .timer = gk20a_timer_new,
 //     .ce[0] = gm204_ce0_new,
        .ltc = gm107_ltc_new,
        .mc = gk20a_mc_new,
        .mmu = gf100_mmu_new,
-//     .mxm = nv50_mxm_new,
+       .mxm = nv50_mxm_new,
 //     .pmu = gk208_pmu_new,
 //     .timer = gk20a_timer_new,
 //     .ce[0] = gm204_ce0_new,
 
        switch (device->chipset) {
        case 0xc0:
                device->oclass[NVDEV_SUBDEV_THERM  ] = >215_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0xc4:
                device->oclass[NVDEV_SUBDEV_THERM  ] = >215_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0xc3:
                device->oclass[NVDEV_SUBDEV_THERM  ] = >215_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0xce:
                device->oclass[NVDEV_SUBDEV_THERM  ] = >215_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0xcf:
                device->oclass[NVDEV_SUBDEV_THERM  ] = >215_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0xc1:
                device->oclass[NVDEV_SUBDEV_THERM  ] = >215_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0xc8:
                device->oclass[NVDEV_SUBDEV_THERM  ] = >215_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0xd9:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &gf110_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gf110_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0xd7:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &gf110_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
                device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
 
        switch (device->chipset) {
        case 0xe4:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &gf110_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gk104_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0xe7:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &gf110_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gf110_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0xe6:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &gf110_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gk104_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0xf0:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &gf110_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gk110_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0xf1:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &gf110_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gk110_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0x106:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &gf110_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gk208_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0x108:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &gf110_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gk208_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 
        switch (device->chipset) {
        case 0x117:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &gm107_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gk208_pmu_oclass;
 
                /* priv ring says no to 0x10eb14 writes */
                device->oclass[NVDEV_SUBDEV_THERM  ] = &gm107_therm_oclass;
 #endif
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gk208_pmu_oclass;
 #if 0
                /* priv ring says no to 0x10eb14 writes */
                device->oclass[NVDEV_SUBDEV_THERM  ] = &gm107_therm_oclass;
 #endif
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gk208_pmu_oclass;
 #if 0
 
        switch (device->chipset) {
        case 0x50:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &nv50_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
                break;
        case 0x84:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
                break;
        case 0x86:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
                break;
        case 0x92:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
                break;
        case 0x94:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
                break;
        case 0x96:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
                break;
        case 0x98:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
                break;
        case 0xa0:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
                break;
        case 0xaa:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
                break;
        case 0xac:
                device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
                break;
        case 0xa3:
                device->oclass[NVDEV_SUBDEV_THERM  ] = >215_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0xa5:
                device->oclass[NVDEV_SUBDEV_THERM  ] = >215_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0xa8:
                device->oclass[NVDEV_SUBDEV_THERM  ] = >215_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                break;
        case 0xaf:
                device->oclass[NVDEV_SUBDEV_THERM  ] = >215_therm_oclass;
-               device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 
        return -ENOENT;
 }
 
+static const struct nvkm_subdev_func
+nvkm_mxm = {
+};
+
 int
-nvkm_mxm_create_(struct nvkm_object *parent, struct nvkm_object *engine,
-                struct nvkm_oclass *oclass, int length, void **pobject)
+nvkm_mxm_new_(struct nvkm_device *device, int index, struct nvkm_mxm **pmxm)
 {
-       struct nvkm_device *device = (void *)parent;
        struct nvkm_bios *bios = device->bios;
        struct nvkm_mxm *mxm;
        u8  ver, len;
        u16 data;
-       int ret;
 
-       ret = nvkm_subdev_create_(parent, engine, oclass, 0, "MXM", "mxm",
-                                 length, pobject);
-       mxm = *pobject;
-       if (ret)
-               return ret;
+       if (!(mxm = *pmxm = kzalloc(sizeof(*mxm), GFP_KERNEL)))
+               return -ENOMEM;
+
+       nvkm_subdev_ctor(&nvkm_mxm, device, index, 0, &mxm->subdev);
 
        data = mxm_table(bios, &ver, &len);
        if (!data || !(ver = nvbios_rd08(bios, data))) {
 
                        return false;
                }
 
-               if (nv_subdev(mxm)->debug >= NV_DBG_DEBUG && (exec == NULL)) {
+               if (mxm->subdev.debug >= NV_DBG_DEBUG && (exec == NULL)) {
                        static const char * mxms_desc[] = {
                                "ODS", "SCCS", "TS", "IPS",
                                "GSD", "VSS", "BCS", "FCS",
 
 #ifndef __NVMXM_MXMS_H__
 #define __NVMXM_MXMS_H__
-#include <subdev/mxm.h>
+#include "priv.h"
 
 struct mxms_odev {
        u8 outp_type;
 
        mxms_foreach(mxm, 0x01, mxm_show_unmatched, NULL);
 }
 
-static int
-nv50_mxm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
-             struct nvkm_oclass *oclass, void *data, u32 size,
-             struct nvkm_object **pobject)
+int
+nv50_mxm_new(struct nvkm_device *device, int index, struct nvkm_subdev **pmxm)
 {
        struct nvkm_mxm *mxm;
        int ret;
 
-       ret = nvkm_mxm_create(parent, engine, oclass, &mxm);
-       *pobject = nv_object(mxm);
+       ret = nvkm_mxm_new_(device, index, &mxm);
+       if (mxm)
+               *pmxm = &mxm->subdev;
        if (ret)
                return ret;
 
        if (mxm->action & MXM_SANITISE_DCB)
                mxm_dcb_sanitise(mxm);
+
        return 0;
 }
-
-struct nvkm_oclass
-nv50_mxm_oclass = {
-       .handle = NV_SUBDEV(MXM, 0x50),
-       .ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = nv50_mxm_ctor,
-               .dtor = _nvkm_mxm_dtor,
-               .init = _nvkm_mxm_init,
-               .fini = _nvkm_mxm_fini,
-       },
-};
 
--- /dev/null
+#ifndef __NVKM_MXM_PRIV_H__
+#define __NVKM_MXM_PRIV_H__
+#define nvkm_mxm(p) container_of((p), struct nvkm_mxm, subdev)
+#include <subdev/mxm.h>
+
+#define MXM_SANITISE_DCB 0x00000001
+
+struct nvkm_mxm {
+       struct nvkm_subdev subdev;
+       u32 action;
+       u8 *mxms;
+};
+
+int nvkm_mxm_new_(struct nvkm_device *, int index, struct nvkm_mxm **);
+#endif