DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
 
        mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
-              SUN4I_TCON_GINT0_VBLANK_ENABLE(1);
+               SUN4I_TCON_GINT0_VBLANK_ENABLE(1) |
+               SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE;
 
        if (enable)
                val = mask;
        regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
 
        if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
-                       SUN4I_TCON_GINT0_VBLANK_INT(1))))
+                       SUN4I_TCON_GINT0_VBLANK_INT(1) |
+                       SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT)))
                return IRQ_NONE;
 
        drm_crtc_handle_vblank(&scrtc->crtc);
        /* Acknowledge the interrupt */
        regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
                           SUN4I_TCON_GINT0_VBLANK_INT(0) |
-                          SUN4I_TCON_GINT0_VBLANK_INT(1),
+                          SUN4I_TCON_GINT0_VBLANK_INT(1) |
+                          SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT,
                           0);
 
        if (engine->ops->vblank_quirk)
 
 
 #define SUN4I_TCON_GINT0_REG                   0x4
 #define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe)           BIT(31 - (pipe))
+#define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE       BIT(27)
+#define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_ENABLE      BIT(26)
 #define SUN4I_TCON_GINT0_VBLANK_INT(pipe)              BIT(15 - (pipe))
+#define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT          BIT(11)
+#define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_INT         BIT(10)
 
 #define SUN4I_TCON_GINT1_REG                   0x8
 #define SUN4I_TCON_FRM_CTL_REG                 0x10