drm/i915/cnl: Add Wa_2201832410

"Clock gating bug in GWL may not clear barrier state when an EOT
is received, causing a hang the next time that barrier is used."

HSDES: 2201832410

Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180307220912.3681-1-rodrigo.vivi@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10580826319e3e5a9c7ab1fe21fa46953cc463bb..9e765462ca44d03c8662641f0a8862e3e10930f1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3965,6 +3965,9 @@ enum {
 #define  SARBUNIT_CLKGATE_DIS          (1 << 5)
 #define  RCCUNIT_CLKGATE_DIS           (1 << 7)
 
+#define SUBSLICE_UNIT_LEVEL_CLKGATE    _MMIO(0x9524)
+#define  GWUNIT_CLKGATE_DIS            (1 << 16)
+
 #define UNSLICE_UNIT_LEVEL_CLKGATE     _MMIO(0x9434)
 #define  VFUNIT_CLKGATE_DIS            (1 << 20)
 

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6cab20ce167ad1c8c005e48fc2989c8be87d3efc..b8da4dcdd584dec02eb3f0316f3ab366f35c8722 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8522,6 +8522,11 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
                val |= SARBUNIT_CLKGATE_DIS;
        I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
 
+       /* Wa_2201832410:cnl */
+       val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
+       val |= GWUNIT_CLKGATE_DIS;
+       I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
+
        /* WaDisableVFclkgate:cnl */
        /* WaVFUnitClockGatingDisable:cnl */
        val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);