arm64: dts: apple: t8010: Add CPU caches

Add information about CPU caches in the P-cluster of Apple A10 SoC. Due to
"Apple Fusion Architecture" big.LITTLE switcher, only caches from one of
the clusters can be used at any given moment.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Link: https://lore.kernel.org/r/20250220-caches-v1-6-2c7011097768@gmail.com
Signed-off-by: Sven Peter <sven@svenpeter.dev>

diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/apple/t8010.dtsi
index 17e294bd7c44c7961cc3ba0ec5f4178840d5b9c6..b961d4f65bc379da3b215ca76d5f68691df06f4d 100644 (file)
--- a/arch/arm64/boot/dts/apple/t8010.dtsi
+++ b/arch/arm64/boot/dts/apple/t8010.dtsi
@@ -36,6 +36,9 @@
                        performance-domains = <&cpufreq>;
                        enable-method = "spin-table";
                        device_type = "cpu";
+                       next-level-cache = <&l2_cache>;
+                       i-cache-size = <0x10000>; /* P-core */
+                       d-cache-size = <0x10000>; /* P-core */
                };
 
                cpu1: cpu@1 {
@@ -46,6 +49,16 @@
                        performance-domains = <&cpufreq>;
                        enable-method = "spin-table";
                        device_type = "cpu";
+                       next-level-cache = <&l2_cache>;
+                       i-cache-size = <0x10000>; /* P-core */
+                       d-cache-size = <0x10000>; /* P-core */
+               };
+
+               l2_cache: l2-cache {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
+                       cache-size = <0x300000>; /* P-cluster */
                };
        };