num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
 
                q_vector->num_ringpairs = num_ringpairs;
+               q_vector->reg_idx = q_vector->v_idx + vsi->base_vector - 1;
 
                q_vector->rx.count = 0;
                q_vector->tx.count = 0;
 
                      I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */
 
                wr32(&vsi->back->hw,
-                    I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1),
+                    I40E_PFINT_DYN_CTLN(q_vector->reg_idx),
                     val);
        } else {
                val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK |
                          /* allow 00 to be written to the index */
 
                wr32(&vsi->back->hw,
-                    I40E_PFINT_DYN_CTLN(q_vector->v_idx +
-                                        vsi->base_vector - 1), val);
+                    I40E_PFINT_DYN_CTLN(q_vector->reg_idx), val);
        } else {
                u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
                          I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
        struct i40e_hw *hw = &vsi->back->hw;
        bool rx = false, tx = false;
        u32 rxval, txval;
-       int vector;
        int idx = q_vector->v_idx;
        int rx_itr_setting, tx_itr_setting;
 
                return;
        }
 
-       vector = (q_vector->v_idx + vsi->base_vector);
-
        /* avoid dynamic calculation if in countdown mode OR if
         * all dynamic is disabled
         */
                 */
                rxval |= BIT(31);
                /* don't check _DOWN because interrupt isn't being enabled */
-               wr32(hw, INTREG(vector - 1), rxval);
+               wr32(hw, INTREG(q_vector->reg_idx), rxval);
        }
 
 enable_int:
        if (!test_bit(__I40E_VSI_DOWN, vsi->state))
-               wr32(hw, INTREG(vector - 1), txval);
+               wr32(hw, INTREG(q_vector->reg_idx), txval);
 
        if (q_vector->itr_countdown)
                q_vector->itr_countdown--;
 
              I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */
 
        wr32(&vsi->back->hw,
-            I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
-                                 vsi->base_vector - 1), val);
+            I40E_VFINT_DYN_CTLN1(q_vector->reg_idx), val);
        q_vector->arm_wb_state = true;
 }
 
                  /* allow 00 to be written to the index */;
 
        wr32(&vsi->back->hw,
-            I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1),
+            I40E_VFINT_DYN_CTLN1(q_vector->reg_idx),
             val);
 }
 
        struct i40e_hw *hw = &vsi->back->hw;
        bool rx = false, tx = false;
        u32 rxval, txval;
-       int vector;
        int idx = q_vector->v_idx;
        int rx_itr_setting, tx_itr_setting;
 
-       vector = (q_vector->v_idx + vsi->base_vector);
-
        /* avoid dynamic calculation if in countdown mode OR if
         * all dynamic is disabled
         */
                 */
                rxval |= BIT(31);
                /* don't check _DOWN because interrupt isn't being enabled */
-               wr32(hw, INTREG(vector - 1), rxval);
+               wr32(hw, INTREG(q_vector->reg_idx), rxval);
        }
 
 enable_int:
        if (!test_bit(__I40E_VSI_DOWN, vsi->state))
-               wr32(hw, INTREG(vector - 1), txval);
+               wr32(hw, INTREG(q_vector->reg_idx), txval);
 
        if (q_vector->itr_countdown)
                q_vector->itr_countdown--;
 
        struct i40evf_adapter *adapter;
        struct i40e_vsi *vsi;
        struct napi_struct napi;
-       unsigned long reg_idx;
        struct i40e_ring_container rx;
        struct i40e_ring_container tx;
        u32 ring_mask;
        u8 num_ringpairs;       /* total number of ring pairs in vector */
 #define ITR_COUNTDOWN_START 100
        u8 itr_countdown;       /* when 0 or 1 update ITR */
-       int v_idx;      /* vector index in list */
+       u16 v_idx;              /* index in the vsi->q_vector array. */
+       u16 reg_idx;            /* register index of the interrupt */
        char name[IFNAMSIZ + 15];
        bool arm_wb_state;
        cpumask_t affinity_mask;
 
                q_vector->adapter = adapter;
                q_vector->vsi = &adapter->vsi;
                q_vector->v_idx = q_idx;
+               q_vector->reg_idx = q_idx;
                cpumask_copy(&q_vector->affinity_mask, cpu_possible_mask);
                netif_napi_add(adapter->netdev, &q_vector->napi,
                               i40evf_napi_poll, NAPI_POLL_WEIGHT);