drm/xe/pcode: Convert register access to use xe_mmio

Stop using GT pointers for register access.  Although some of the pcode
mailboxes are related to GTs, pcode itself (and the register interface
to access it) are outside the GT and should be accessed through the
tile's MMIO.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240910234719.3335472-56-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
index 7397d556996ad4dad88579129f47bae49bfc580e..d95d9835de4238e1894a1f5839795f82feca3e49 100644 (file)
--- a/drivers/gpu/drm/xe/xe_pcode.c
+++ b/drivers/gpu/drm/xe/xe_pcode.c
@@ -44,7 +44,7 @@ static int pcode_mailbox_status(struct xe_tile *tile)
                [PCODE_ERROR_MASK] = {-EPROTO, "Unknown"},
        };
 
-       err = xe_mmio_read32(tile->primary_gt, PCODE_MAILBOX) & PCODE_ERROR_MASK;
+       err = xe_mmio_read32(&tile->mmio, PCODE_MAILBOX) & PCODE_ERROR_MASK;
        if (err) {
                drm_err(&tile_to_xe(tile)->drm, "PCODE Mailbox failed: %d %s", err,
                        err_decode[err].str ?: "Unknown");
@@ -58,7 +58,7 @@ static int __pcode_mailbox_rw(struct xe_tile *tile, u32 mbox, u32 *data0, u32 *d
                              unsigned int timeout_ms, bool return_data,
                              bool atomic)
 {
-       struct xe_gt *mmio = tile->primary_gt;
+       struct xe_mmio *mmio = &tile->mmio;
        int err;
 
        if (tile_to_xe(tile)->info.skip_pcode)