};
 #endif
 
+#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
+static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
+       {
+               ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
+       },
+       {
+               .midr_range.model = MIDR_QCOM_KRYO,
+               .matches = is_kryo_midr,
+       },
+       {},
+};
+#endif
+
 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
 static const struct midr_range workaround_clean_cache[] = {
 #if    defined(CONFIG_ARM64_ERRATUM_826319) || \
        },
 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
        {
-               .desc = "Qualcomm Technologies Falkor erratum 1003",
+               .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
                .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
-               ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
-       },
-       {
-               .desc = "Qualcomm Technologies Kryo erratum 1003",
-               .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
-               .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
-               .midr_range.model = MIDR_QCOM_KRYO,
-               .matches = is_kryo_midr,
+               .matches = multi_entry_cap_matches,
+               .match_list = qcom_erratum_1003_list,
        },
 #endif
 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009