RISC-V: Use WRITE_ONCE instead of direct access

The secondary harts spin on couple of per cpu variables until both of
these are non-zero so it's not necessary to have any ordering here.
However, WRITE_ONCE should be used to avoid tearing.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 17e748312afd5aeec9370bb0fee6cbabe1321296..1e478615017c84b47a560a3077d2b83b65cf5fb0 100644 (file)
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -81,8 +81,9 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle)
         * the spinning harts that they can continue the boot process.
         */
        smp_mb();
-       __cpu_up_stack_pointer[cpu] = task_stack_page(tidle) + THREAD_SIZE;
-       __cpu_up_task_pointer[cpu] = tidle;
+       WRITE_ONCE(__cpu_up_stack_pointer[cpu],
+                 task_stack_page(tidle) + THREAD_SIZE);
+       WRITE_ONCE(__cpu_up_task_pointer[cpu], tidle);
 
        while (!cpu_online(cpu))
                cpu_relax();