clk: samsung: Pull struct exynos_cpuclk into clk-cpu.c

Reduce the scope of struct exynos_cpuclk, as it's only used in clk-cpu.c
internally. All drivers using clk-pll.h already include clk.h as well,
so this change doesn't break anything.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-4-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index e02730776aaa1ea5ad0d172b4b94df270b383291..6412fd2580e01f8497819c4b77a2b8595ca0199a 100644 (file)
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -34,6 +34,8 @@
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
+
+#include "clk.h"
 #include "clk-cpu.h"
 
 #define E4210_SRC_CPU          0x0
@@ -64,6 +66,33 @@
 #define DIV_MASK_ALL           GENMASK(31, 0)
 #define MUX_MASK               GENMASK(2, 0)
 
+/**
+ * struct exynos_cpuclk - information about clock supplied to a CPU core
+ * @hw:                handle between CCF and CPU clock
+ * @alt_parent:        alternate parent clock to use when switching the speed
+ *             of the primary parent clock
+ * @ctrl_base: base address of the clock controller
+ * @lock:      cpu clock domain register access lock
+ * @cfg:       cpu clock rate configuration data
+ * @num_cfgs:  number of array elements in @cfg array
+ * @clk_nb:    clock notifier registered for changes in clock speed of the
+ *             primary parent clock
+ * @flags:     configuration flags for the CPU clock
+ *
+ * This structure holds information required for programming the CPU clock for
+ * various clock speeds.
+ */
+struct exynos_cpuclk {
+       struct clk_hw                           hw;
+       const struct clk_hw                     *alt_parent;
+       void __iomem                            *ctrl_base;
+       spinlock_t                              *lock;
+       const struct exynos_cpuclk_cfg_data     *cfg;
+       const unsigned long                     num_cfgs;
+       struct notifier_block                   clk_nb;
+       unsigned long                           flags;
+};
+
 /*
  * Helper function to wait until divider(s) have stabilized after the divider
  * value has changed.

diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h
index 0164bd9ad021b915eb3efdcbb805b9210e580d26..ee57f3638fedeb65434892194e136866e146f412 100644 (file)
--- a/drivers/clk/samsung/clk-cpu.h
+++ b/drivers/clk/samsung/clk-cpu.h
@@ -8,7 +8,12 @@
 #ifndef __SAMSUNG_CLK_CPU_H
 #define __SAMSUNG_CLK_CPU_H
 
-#include "clk.h"
+/* The CPU clock registers have DIV1 configuration register */
+#define CLK_CPU_HAS_DIV1               BIT(0)
+/* When ALT parent is active, debug clocks need safe divider values */
+#define CLK_CPU_NEEDS_DEBUG_ALT_DIV    BIT(1)
+/* The CPU clock registers have Exynos5433-compatible layout */
+#define CLK_CPU_HAS_E5433_REGS_LAYOUT  BIT(2)
 
 /**
  * struct exynos_cpuclk_cfg_data - config data to setup cpu clocks
@@ -28,38 +33,4 @@ struct exynos_cpuclk_cfg_data {
        unsigned long   div1;
 };
 
-/**
- * struct exynos_cpuclk - information about clock supplied to a CPU core
- * @hw:                handle between CCF and CPU clock
- * @alt_parent:        alternate parent clock to use when switching the speed
- *             of the primary parent clock
- * @ctrl_base: base address of the clock controller
- * @lock:      cpu clock domain register access lock
- * @cfg:       cpu clock rate configuration data
- * @num_cfgs:  number of array elements in @cfg array
- * @clk_nb:    clock notifier registered for changes in clock speed of the
- *             primary parent clock
- * @flags:     configuration flags for the CPU clock
- *
- * This structure holds information required for programming the CPU clock for
- * various clock speeds.
- */
-struct exynos_cpuclk {
-       struct clk_hw                           hw;
-       const struct clk_hw                     *alt_parent;
-       void __iomem                            *ctrl_base;
-       spinlock_t                              *lock;
-       const struct exynos_cpuclk_cfg_data     *cfg;
-       const unsigned long                     num_cfgs;
-       struct notifier_block                   clk_nb;
-       unsigned long                           flags;
-
-/* The CPU clock registers have DIV1 configuration register */
-#define CLK_CPU_HAS_DIV1               (1 << 0)
-/* When ALT parent is active, debug clocks need safe divider values */
-#define CLK_CPU_NEEDS_DEBUG_ALT_DIV    (1 << 1)
-/* The CPU clock registers have Exynos5433-compatible layout */
-#define CLK_CPU_HAS_E5433_REGS_LAYOUT  (1 << 2)
-};
-
 #endif /* __SAMSUNG_CLK_CPU_H */