drm/amd/display: Passing Y-granularity to dmub fw

[Why]
The Y-granularity panel parameter indicate the grid
pattern granularity in the Y direction for PSRSU.

[How]
Send the Y-granularity data by PSR_COPY_SETTINGS dmub command.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 97bb2d8764269265b4beff4e2fc341e6ab5b1cc4..dc1d75b204cde45f328ffeed6ea847d0ca388b98 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3270,6 +3270,10 @@ bool dc_link_setup_psr(struct dc_link *link,
                        DP_RECEIVER_ALPM_CONFIG,
                        &alpm_configuration.raw,
                        sizeof(alpm_configuration.raw));
+               psr_context->su_granularity_required =
+                       psr_config->su_granularity_required;
+               psr_context->su_y_granularity =
+                       psr_config->su_y_granularity;
        }
 
        psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 2ba9f528c0fe7205fe13648b464bdc5eba6c87ff..d61ea3e2bfbfb6cc5fd527ff422feb2fa38a4f65 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -672,6 +672,10 @@ struct psr_config {
        unsigned int psr_sdp_transmit_line_num_deadline;
        bool allow_smu_optimizations;
        bool allow_multi_disp_optimizations;
+       /* Panel self refresh 2 selective update granularity required */
+       bool su_granularity_required;
+       /* psr2 selective update y granularity capability */
+       uint8_t su_y_granularity;
 };
 
 union dmcu_psr_level {
@@ -775,6 +779,10 @@ struct psr_context {
        unsigned int frame_delay;
        bool allow_smu_optimizations;
        bool allow_multi_disp_optimizations;
+       /* Panel self refresh 2 selective update granularity required */
+       bool su_granularity_required;
+       /* psr2 selective update y granularity capability */
+       uint8_t su_y_granularity;
 };
 
 struct colorspace_transform {

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index f1411a22cf1ecd95ec017bf321b86a4a8b0ff3e7..6883dd5b80d66cc53b30ce07f7a6f3e4ba997ca5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -333,6 +333,12 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
        copy_settings_data->debug.u32All = 0;
        copy_settings_data->debug.bitfields.visual_confirm      = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
        copy_settings_data->debug.bitfields.use_hw_lock_mgr             = 1;
+
+       if (psr_context->su_granularity_required == 0)
+               copy_settings_data->su_y_granularity = 0;
+       else
+               copy_settings_data->su_y_granularity = psr_context->su_y_granularity;
+
        copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
        copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
        copy_settings_data->cmd_version =  DMUB_CMD_PSR_CONTROL_VERSION_1;