drm/amd/display: Replay low hz

[Why]
The original coasting vtotal is 2 bytes, and it need to be amended to 4
bytes because low hz case.

[How]
Amend coasting vtotal from 2 bytes to 4 bytes.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: ChunTao Tso <ChunTao.Tso@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
index b9769181269d542c933b25be2ea3850bf6e67688..fd91445d4d8e6125e897eef07967f079a1660cba 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
@@ -216,17 +216,21 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub,
  * Set coasting vtotal.
  */
 static void dmub_replay_set_coasting_vtotal(struct dmub_replay *dmub,
-               uint16_t coasting_vtotal,
+               uint32_t coasting_vtotal,
                uint8_t panel_inst)
 {
        union dmub_rb_cmd cmd;
        struct dc_context *dc = dmub->ctx;
+       struct dmub_rb_cmd_replay_set_coasting_vtotal *pCmd = NULL;
+
+       pCmd = &(cmd.replay_set_coasting_vtotal);
 
        memset(&cmd, 0, sizeof(cmd));
-       cmd.replay_set_coasting_vtotal.header.type = DMUB_CMD__REPLAY;
-       cmd.replay_set_coasting_vtotal.header.sub_type = DMUB_CMD__REPLAY_SET_COASTING_VTOTAL;
-       cmd.replay_set_coasting_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_replay_set_coasting_vtotal_data);
-       cmd.replay_set_coasting_vtotal.replay_set_coasting_vtotal_data.coasting_vtotal = coasting_vtotal;
+       pCmd->header.type = DMUB_CMD__REPLAY;
+       pCmd->header.sub_type = DMUB_CMD__REPLAY_SET_COASTING_VTOTAL;
+       pCmd->header.payload_bytes = sizeof(struct dmub_cmd_replay_set_coasting_vtotal_data);
+       pCmd->replay_set_coasting_vtotal_data.coasting_vtotal = (coasting_vtotal & 0xFFFF);
+       pCmd->replay_set_coasting_vtotal_data.coasting_vtotal_high = (coasting_vtotal & 0xFFFF0000) >> 16;
 
        dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 }
@@ -259,20 +263,22 @@ static void dmub_replay_residency(struct dmub_replay *dmub, uint8_t panel_inst,
  * Set REPLAY power optimization flags and coasting vtotal.
  */
 static void dmub_replay_set_power_opt_and_coasting_vtotal(struct dmub_replay *dmub,
-               unsigned int power_opt, uint8_t panel_inst, uint16_t coasting_vtotal)
+               unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal)
 {
        union dmub_rb_cmd cmd;
        struct dc_context *dc = dmub->ctx;
+       struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal *pCmd = NULL;
+
+       pCmd = &(cmd.replay_set_power_opt_and_coasting_vtotal);
 
        memset(&cmd, 0, sizeof(cmd));
-       cmd.replay_set_power_opt_and_coasting_vtotal.header.type = DMUB_CMD__REPLAY;
-       cmd.replay_set_power_opt_and_coasting_vtotal.header.sub_type =
-               DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL;
-       cmd.replay_set_power_opt_and_coasting_vtotal.header.payload_bytes =
-               sizeof(struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal);
-       cmd.replay_set_power_opt_and_coasting_vtotal.replay_set_power_opt_data.power_opt = power_opt;
-       cmd.replay_set_power_opt_and_coasting_vtotal.replay_set_power_opt_data.panel_inst = panel_inst;
-       cmd.replay_set_power_opt_and_coasting_vtotal.replay_set_coasting_vtotal_data.coasting_vtotal = coasting_vtotal;
+       pCmd->header.type = DMUB_CMD__REPLAY;
+       pCmd->header.sub_type = DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL;
+       pCmd->header.payload_bytes = sizeof(struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal);
+       pCmd->replay_set_power_opt_data.power_opt = power_opt;
+       pCmd->replay_set_power_opt_data.panel_inst = panel_inst;
+       pCmd->replay_set_coasting_vtotal_data.coasting_vtotal = (coasting_vtotal & 0xFFFF);
+       pCmd->replay_set_coasting_vtotal_data.coasting_vtotal_high = (coasting_vtotal & 0xFFFF0000) >> 16;
 
        dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
index 3613aff994d725362dabd5e5cbb75cfc576d1a52..d090ec900c080880f5e35baf459a110c5b7956b5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
@@ -47,12 +47,12 @@ struct dmub_replay_funcs {
                uint8_t panel_inst);
        void (*replay_send_cmd)(struct dmub_replay *dmub,
                enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_element);
-       void (*replay_set_coasting_vtotal)(struct dmub_replay *dmub, uint16_t coasting_vtotal,
+       void (*replay_set_coasting_vtotal)(struct dmub_replay *dmub, uint32_t coasting_vtotal,
                uint8_t panel_inst);
        void (*replay_residency)(struct dmub_replay *dmub,
                uint8_t panel_inst, uint32_t *residency, const bool is_start, const bool is_alpm);
        void (*replay_set_power_opt_and_coasting_vtotal)(struct dmub_replay *dmub,
-               unsigned int power_opt, uint8_t panel_inst, uint16_t coasting_vtotal);
+               unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal);
 };
 
 struct dmub_replay *dmub_replay_create(struct dc_context *ctx);

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 36c15ae43616d30cab84f4cbeebde7cabb117694..fe529b67369e491b4a21d7f4b40c9c0154736cb8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -3004,6 +3004,14 @@ struct dmub_cmd_update_dirty_rect_data {
         * Currently the support is only for 0 or 1
         */
        uint8_t panel_inst;
+       /**
+        * 16-bit value dicated by driver that indicates the coasting vtotal high byte part.
+        */
+       uint16_t coasting_vtotal_high;
+       /**
+        * Explicit padding to 4 byte boundary.
+        */
+       uint8_t pad[2];
 };
 
 /**