drm/xe: Rename MCFG_MCR_SELECTOR to STEER_SEMAPHORE

The register at offset 0xfd0 was incorrectly named MCFG_MCR_SELECTOR,
likely copied from i915. According to the hardware specification (Bspec),
this register is actually called STEER_SEMAPHORE.

Rename the register definition and update its usage in xe_gt_mcr.c to
match the official hardware documentation.

No functional changes.

v2: Add Bspec reference (Tejas)

Bspec: 67113
Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Link: https://lore.kernel.org/r/20250723141039.3848390-1-nitin.r.gote@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 5cd5ab8529c5c07c396c9d2a588d7361fcd549e5..f96b2e2b30645de3e6efb8ba3c791d407af51960 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -42,7 +42,7 @@
 #define FORCEWAKE_ACK_GSC                      XE_REG(0xdf8)
 #define FORCEWAKE_ACK_GT_MTL                   XE_REG(0xdfc)
 
-#define MCFG_MCR_SELECTOR                      XE_REG(0xfd0)
+#define STEER_SEMAPHORE                                XE_REG(0xfd0)
 #define MTL_MCR_SELECTOR                       XE_REG(0xfd4)
 #define SF_MCR_SELECTOR                                XE_REG(0xfd8)
 #define MCR_SELECTOR                           XE_REG(0xfdc)

diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 64a2f0d6aaf95f492a7867e42360f580024fb37d..683ac021a06dadd9f411e8bb3c5597e243904fa2 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -46,8 +46,6 @@
  * MCR registers are not available on Virtual Function (VF).
  */
 
-#define STEER_SEMAPHORE                XE_REG(0xFD0)
-
 static inline struct xe_reg to_xe_reg(struct xe_reg_mcr reg_mcr)
 {
        return reg_mcr.__reg;
@@ -533,7 +531,7 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
                u32 steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, 0) |
                        REG_FIELD_PREP(MCR_SUBSLICE_MASK, 2);
 
-               xe_mmio_write32(&gt->mmio, MCFG_MCR_SELECTOR, steer_val);
+               xe_mmio_write32(&gt->mmio, STEER_SEMAPHORE, steer_val);
                xe_mmio_write32(&gt->mmio, SF_MCR_SELECTOR, steer_val);
                /*
                 * For GAM registers, all reads should be directed to instance 1