return mp_affinity;
}
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
- unsigned long ram_size)
+Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
{
int i, n;
Exynos4210State *s = g_new(Exynos4210State, 1);
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
- unsigned long mem_size;
DeviceState *dev;
SysBusDevice *busdev;
ObjectClass *cpu_oc;
memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
&s->iram_mem);
- /* DRAM */
- mem_size = ram_size;
- if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
- memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
- mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal);
- vmstate_register_ram_global(&s->dram1_mem);
- memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
- &s->dram1_mem);
- mem_size = EXYNOS4210_DRAM_MAX_SIZE;
- }
- memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
- &error_fatal);
- vmstate_register_ram_global(&s->dram0_mem);
- memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
- &s->dram0_mem);
-
/* PMU.
* The only reason of existence at the moment is that secondary CPU boot
* loader uses PMU INFORM5 register as a holding pen.
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu-common.h"
#include "cpu.h"
EXYNOS4_NUM_OF_BOARDS
} Exynos4BoardType;
+typedef struct Exynos4BoardState {
+ Exynos4210State *soc;
+ MemoryRegion dram0_mem;
+ MemoryRegion dram1_mem;
+} Exynos4BoardState;
+
static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = {
[EXYNOS4_BOARD_NURI] = 0xD33,
[EXYNOS4_BOARD_SMDKC210] = 0xB16,
}
}
-static Exynos4210State *exynos4_boards_init_common(MachineState *machine,
- Exynos4BoardType board_type)
+static void exynos4_boards_init_ram(Exynos4BoardState *s,
+ MemoryRegion *system_mem,
+ unsigned long ram_size)
+{
+ unsigned long mem_size = ram_size;
+
+ if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
+ memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
+ mem_size - EXYNOS4210_DRAM_MAX_SIZE,
+ &error_fatal);
+ vmstate_register_ram_global(&s->dram1_mem);
+ memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
+ &s->dram1_mem);
+ mem_size = EXYNOS4210_DRAM_MAX_SIZE;
+ }
+
+ memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
+ &error_fatal);
+ vmstate_register_ram_global(&s->dram0_mem);
+ memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
+ &s->dram0_mem);
+}
+
+static Exynos4BoardState *
+exynos4_boards_init_common(MachineState *machine,
+ Exynos4BoardType board_type)
{
+ Exynos4BoardState *s = g_new(Exynos4BoardState, 1);
MachineClass *mc = MACHINE_GET_CLASS(machine);
if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) {
machine->kernel_cmdline,
machine->initrd_filename);
- return exynos4210_init(get_system_memory(),
- exynos4_board_ram_size[board_type]);
+ exynos4_boards_init_ram(s, get_system_memory(),
+ exynos4_board_ram_size[board_type]);
+
+ s->soc = exynos4210_init(get_system_memory());
+
+ return s;
}
static void nuri_init(MachineState *machine)
static void smdkc210_init(MachineState *machine)
{
- Exynos4210State *s = exynos4_boards_init_common(machine,
- EXYNOS4_BOARD_SMDKC210);
+ Exynos4BoardState *s = exynos4_boards_init_common(machine,
+ EXYNOS4_BOARD_SMDKC210);
lan9215_init(SMDK_LAN9118_BASE_ADDR,
- qemu_irq_invert(s->irq_table[exynos4210_get_irq(37, 1)]));
+ qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
}
MemoryRegion iram_mem;
MemoryRegion irom_mem;
MemoryRegion irom_alias_mem;
- MemoryRegion dram0_mem;
- MemoryRegion dram1_mem;
MemoryRegion boot_secondary;
MemoryRegion bootreg_mem;
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
void exynos4210_write_secondary(ARMCPU *cpu,
const struct arm_boot_info *info);
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
- unsigned long ram_size);
+Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
/* Initialize exynos4210 IRQ subsystem stub */
qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);