riscv: dts: starfive: fml13v01: enable USB 3.0 port

Add usb_cdns3 and usb0_pins configuration to support super speed USB
device on the FML13V01 board.

Signed-off-by: Sandie Cao <sandie.cao@deepcomputing.io>
Tested-by: Maud Spierings <maud_spierings@hotmail.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
index 8d9ce8b69a71be78ca57618ae842c9f415648450..f2857d021d6812197dae5460a64dbc53155959a1 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
@@ -43,9 +43,28 @@
                        slew-rate = <0>;
                };
        };
+
+       usb0_pins: usb0-0 {
+               vbus-pins {
+                       pinmux = <GPIOMUX(25,  GPOUT_SYS_USB_DRIVE_VBUS,
+                                              GPOEN_ENABLE,
+                                              GPI_NONE)>;
+                       bias-disable;
+                       input-disable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+       };
 };
 
 &usb0 {
        dr_mode = "host";
+       pinctrl-names = "default";
+       pinctrl-0 = <&usb0_pins>;
        status = "okay";
 };
+
+&usb_cdns3 {
+       phys = <&usbphy0>, <&pciephy0>;
+       phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
+};