ENA_ADMIN_FEATURES_OPCODE_NUM               = 32,
 };
 
+/* device capabilities */
+enum ena_admin_aq_caps_id {
+       ENA_ADMIN_ENI_STATS                         = 0,
+};
+
 enum ena_admin_placement_policy_type {
        /* descriptors and headers are in host memory */
        ENA_ADMIN_PLACEMENT_POLICY_HOST             = 1,
         */
        u32 supported_features;
 
-       u32 reserved3;
+       /* bitmap of ena_admin_aq_caps_id, which represents device
+        * capabilities.
+        */
+       u32 capabilities;
 
        /* Indicates how many bits are used physical address access. */
        u32 phys_addr_width;
 
               sizeof(get_resp.u.dev_attr));
 
        ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
+       ena_dev->capabilities = get_resp.u.dev_attr.capabilities;
 
        if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
                rc = ena_com_get_feature(ena_dev, &get_resp,
        struct ena_com_stats_ctx ctx;
        int ret;
 
+       if (!ena_com_get_cap(ena_dev, ENA_ADMIN_ENI_STATS)) {
+               netdev_err(ena_dev->net_device,
+                          "Capability %d isn't supported\n",
+                          ENA_ADMIN_ENI_STATS);
+               return -EOPNOTSUPP;
+       }
+
        memset(&ctx, 0x0, sizeof(ctx));
        ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENI);
        if (likely(ret == 0))
 
 
        struct ena_rss rss;
        u32 supported_features;
+       u32 capabilities;
        u32 dma_addr_bits;
 
        struct ena_host_attribute host_attr;
        ena_dev->adaptive_coalescing = false;
 }
 
+/* ena_com_get_cap - query whether device supports a capability.
+ * @ena_dev: ENA communication layer struct
+ * @cap_id: enum value representing the capability
+ *
+ * @return - true if capability is supported or false otherwise
+ */
+static inline bool ena_com_get_cap(struct ena_com_dev *ena_dev,
+                                  enum ena_admin_aq_caps_id cap_id)
+{
+       return !!(ena_dev->capabilities & BIT(cap_id));
+}
+
 /* ena_com_update_intr_reg - Prepare interrupt register
  * @intr_reg: interrupt register to update.
  * @rx_delay_interval: Rx interval in usecs