drm/amd/display: add dscclk instance offset check

[why]
based on dscclk instance offset check conditiona program dscclk

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index 893c0809cd4e0c64d76cf719720c26d219f56135..7bdc146f7cb59810209f058e11c17be633b09762 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -205,6 +205,11 @@
        type PHYDSYMCLK_GATE_DISABLE; \
        type PHYESYMCLK_GATE_DISABLE;
 
+#define DCCG314_REG_FIELD_LIST(type) \
+       type DSCCLK3_DTO_PHASE;\
+       type DSCCLK3_DTO_MODULO;\
+       type DSCCLK3_DTO_ENABLE;
+
 #define DCCG32_REG_FIELD_LIST(type) \
        type DPSTREAMCLK0_EN;\
        type DPSTREAMCLK1_EN;\
@@ -237,6 +242,7 @@ struct dccg_shift {
        DCCG_REG_FIELD_LIST(uint8_t)
        DCCG3_REG_FIELD_LIST(uint8_t)
        DCCG31_REG_FIELD_LIST(uint8_t)
+       DCCG314_REG_FIELD_LIST(uint8_t)
        DCCG32_REG_FIELD_LIST(uint8_t)
 };
 
@@ -244,6 +250,7 @@ struct dccg_mask {
        DCCG_REG_FIELD_LIST(uint32_t)
        DCCG3_REG_FIELD_LIST(uint32_t)
        DCCG31_REG_FIELD_LIST(uint32_t)
+       DCCG314_REG_FIELD_LIST(uint32_t)
        DCCG32_REG_FIELD_LIST(uint32_t)
 };
 
@@ -273,6 +280,7 @@ struct dccg_registers {
        uint32_t DSCCLK0_DTO_PARAM;
        uint32_t DSCCLK1_DTO_PARAM;
        uint32_t DSCCLK2_DTO_PARAM;
+       uint32_t DSCCLK3_DTO_PARAM;
        uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;
        uint32_t DPSTREAMCLK_GATE_DISABLE;
        uint32_t DCCG_GATE_DISABLE_CNTL;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 7d2b982506fd7ba9e820002cbee2a74e23adc461..4c2fdfea162f55cb567e2ac702936221d70eec1a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -360,6 +360,15 @@ void dccg31_disable_dscclk(struct dccg *dccg, int inst)
                                DSCCLK2_DTO_PHASE, 0,
                                DSCCLK2_DTO_MODULO, 1);
                break;
+       case 3:
+               if (REG(DSCCLK3_DTO_PARAM)) {
+                       REG_UPDATE(DSCCLK_DTO_CTRL,
+                                       DSCCLK3_DTO_ENABLE, 1);
+                       REG_UPDATE_2(DSCCLK3_DTO_PARAM,
+                                       DSCCLK3_DTO_PHASE, 0,
+                                       DSCCLK3_DTO_MODULO, 1);
+               }
+               break;
        default:
                BREAK_TO_DEBUGGER();
                return;
@@ -395,6 +404,15 @@ void dccg31_enable_dscclk(struct dccg *dccg, int inst)
                REG_UPDATE(DSCCLK_DTO_CTRL,
                                DSCCLK2_DTO_ENABLE, 0);
                break;
+       case 3:
+               if (REG(DSCCLK3_DTO_PARAM)) {
+                       REG_UPDATE(DSCCLK_DTO_CTRL,
+                                       DSCCLK3_DTO_ENABLE, 0);
+                       REG_UPDATE_2(DSCCLK3_DTO_PARAM,
+                                       DSCCLK3_DTO_PHASE, 0,
+                                       DSCCLK3_DTO_MODULO, 0);
+               }
+               break;
        default:
                BREAK_TO_DEBUGGER();
                return;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h
index f62631ab53a27c9b87877e6b625434e542553b14..90687a9e8fdddf451fc9b8363ae7dced0065331b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h
@@ -68,6 +68,7 @@
        SR(DSCCLK0_DTO_PARAM),\
        SR(DSCCLK1_DTO_PARAM),\
        SR(DSCCLK2_DTO_PARAM),\
+       SR(DSCCLK3_DTO_PARAM),\
        SR(DSCCLK_DTO_CTRL),\
        SR(DCCG_GATE_DISABLE_CNTL2),\
        SR(DCCG_GATE_DISABLE_CNTL3),\
@@ -149,6 +150,8 @@
        DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\
        DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\
        DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\
+       DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_PHASE, mask_sh),\
+       DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_MODULO, mask_sh),\
        DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\
        DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\
        DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
@@ -184,6 +187,7 @@
        DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, mask_sh),\
        DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, mask_sh),\
        DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh),\
+       DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK3_DTO_ENABLE, mask_sh),\
        DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, mask_sh),\
        DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, mask_sh),\
        DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\