if (uart_circ_empty(&port->state->xmit)) {
                writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
-       } else {
-               numbytes = port->fifosize;
-               while (numbytes && !uart_circ_empty(&port->state->xmit) &&
-                      !(readl(port->membase + CDNS_UART_SR) &
-                                               CDNS_UART_SR_TXFULL)) {
-                       /*
-                        * Get the data from the UART circular buffer
-                        * and write it to the cdns_uart's TX_FIFO
-                        * register.
-                        */
-                       writel(
-                               port->state->xmit.buf[port->state->xmit.tail],
-                                       port->membase + CDNS_UART_FIFO);
-
-                       port->icount.tx++;
-
-                       /*
-                        * Adjust the tail of the UART buffer and wrap
-                        * the buffer if it reaches limit.
-                        */
-                       port->state->xmit.tail =
-                               (port->state->xmit.tail + 1) &
-                                       (UART_XMIT_SIZE - 1);
-
-                       numbytes--;
-               }
+               return;
+       }
 
-               if (uart_circ_chars_pending(
-                               &port->state->xmit) < WAKEUP_CHARS)
-                       uart_write_wakeup(port);
+       numbytes = port->fifosize;
+       while (numbytes && !uart_circ_empty(&port->state->xmit) &&
+              !(readl(port->membase + CDNS_UART_SR) &
+                                       CDNS_UART_SR_TXFULL)) {
+
+               writel(port->state->xmit.buf[port->state->xmit.tail],
+                               port->membase + CDNS_UART_FIFO);
+
+               port->icount.tx++;
+               port->state->xmit.tail = (port->state->xmit.tail + 1) &
+                               (UART_XMIT_SIZE - 1);
+
+               numbytes--;
        }
+
+       if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
+               uart_write_wakeup(port);
 }
 
 /**