clk: renesas: r9a07g044: Add clock and reset entries for CRU

Add CRU clock and reset entries to CPG driver.

CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular
sequence for the CRU block hence add these clocks to
r9a07g044_no_pm_mod_clks[] array and pass it as part of CPG data for
both RZ/G2L and RZ/V2L SoCs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221221212703.348278-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index f5550fccb029cad839d88bf0b159188288e5c7ff..c597414a94d8a0345024a7fe4ab5d6b5e6387f23 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -182,7 +182,7 @@ static const struct {
 };
 
 static const struct {
-       struct rzg2l_mod_clk common[75];
+       struct rzg2l_mod_clk common[79];
 #ifdef CONFIG_CLK_R9A07G054
        struct rzg2l_mod_clk drp[0];
 #endif
@@ -250,6 +250,14 @@ static const struct {
                                        0x558, 1),
                DEF_MOD("gpu_ace_clk",  R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
                                        0x558, 2),
+               DEF_MOD("cru_sysclk",   R9A07G044_CRU_SYSCLK, CLK_M2_DIV2,
+                                       0x564, 0),
+               DEF_MOD("cru_vclk",     R9A07G044_CRU_VCLK, R9A07G044_CLK_M2,
+                                       0x564, 1),
+               DEF_MOD("cru_pclk",     R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT,
+                                       0x564, 2),
+               DEF_MOD("cru_aclk",     R9A07G044_CRU_ACLK, R9A07G044_CLK_M0,
+                                       0x564, 3),
                DEF_MOD("dsi_pll_clk",  R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,
                                        0x568, 0),
                DEF_MOD("dsi_sys_clk",  R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2,
@@ -368,6 +376,9 @@ static struct rzg2l_reset r9a07g044_resets[] = {
        DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
        DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
        DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
+       DEF_RST(R9A07G044_CRU_CMN_RSTB, 0x864, 0),
+       DEF_RST(R9A07G044_CRU_PRESETN, 0x864, 1),
+       DEF_RST(R9A07G044_CRU_ARESETN, 0x864, 2),
        DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0),
        DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1),
        DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2),
@@ -412,6 +423,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
        MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
 };
 
+static const unsigned int r9a07g044_no_pm_mod_clks[] = {
+       MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
+       MOD_CLK_BASE + R9A07G044_CRU_VCLK,
+};
+
 #ifdef CONFIG_CLK_R9A07G044
 const struct rzg2l_cpg_info r9a07g044_cpg_info = {
        /* Core Clocks */
@@ -429,6 +445,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
        .num_mod_clks = ARRAY_SIZE(mod_clks.common),
        .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
 
+       /* No PM Module Clocks */
+       .no_pm_mod_clks = r9a07g044_no_pm_mod_clks,
+       .num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks),
+
        /* Resets */
        .resets = r9a07g044_resets,
        .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
@@ -454,6 +474,10 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = {
        .num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp),
        .num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1,
 
+       /* No PM Module Clocks */
+       .no_pm_mod_clks = r9a07g044_no_pm_mod_clks,
+       .num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks),
+
        /* Resets */
        .resets = r9a07g044_resets,
        .num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */