#define AMD_PG_SUPPORT_GFX_PIPELINE            (1 << 12)
 #define AMD_PG_SUPPORT_MMHUB                   (1 << 13)
 #define AMD_PG_SUPPORT_VCN                     (1 << 14)
-#define AMD_PG_SUPPORT_VCN_DPG (1 << 15)
+#define AMD_PG_SUPPORT_VCN_DPG                 (1 << 15)
+#define AMD_PG_SUPPORT_ATHUB                   (1 << 16)
 
 enum PP_FEATURE_MASK {
        PP_SCLK_DPM_MASK = 0x1,
 
                                | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
                                | FEATURE_MASK(FEATURE_THERMAL_BIT)
                                | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
-                               | FEATURE_MASK(FEATURE_ATHUB_PG_BIT)
                                | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
                                | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
                                | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
        if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 
+       if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
+               *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
+
        if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);