drm/xe/gsc: define GSCCS for LNL

LNL has 1 GSCCS, same as MTL. Note that the GSCCS will be disabled until
we have a GSC FW defined, but having it in the list of engine is a
requirement to add such definition.

v2: rebase

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240419183412.1605782-2-daniele.ceraolospurio@intel.com

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index fb20c98285633834eeb437536c68c275be6c08a7..d0d4d8f9749c70c02f9521752d446668f7072a90 100644 (file)
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -211,7 +211,8 @@ static const struct xe_media_desc media_xe2 = {
        .name = "Xe2_LPM / Xe2_HPM",
        .hw_engine_mask =
                GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
-               GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), /* TODO: GSC0 */
+               GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) |
+               BIT(XE_HW_ENGINE_GSCCS0)
 };
 
 static const struct xe_device_desc tgl_desc = {