x86/cpufeatures: rename X86_FEATURE_AMD_SSBD to X86_FEATURE_LS_CFG_SSBD

The commit 52817587e706 ('x86/cpufeatures: Disentangle SSBD enumeration') from
upstream disentangles SSBD enumeration. We did not backport that commit because
we did not have what to disentangle on UEK4. Our cpufeature was already
synthetic.

That commit also renames X86_FEATURE_AMD_SSBD to X86_FEATURE_LS_CFG_SSBD. We
need this rename in order to not have conflicting cpu features while
backporting commit 6ac2f49edb1e ('x86/bugs: Add AMD's SPEC_CTRL MSR usage')
from upstream which introduces SPEC_CTRL MSR, which will be the prefered
method.

Orabug: 28870524
CVE: CVE-2018-3639

Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Signed-off-by: Brian Maly <brian.maly@oracle.com>

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 403322a3ce0b781f7063475c2f0487062d2541b4..edf15b54395c499631874237bee1d033c2103db7 100644 (file)
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -201,7 +201,7 @@
 #define X86_FEATURE_INTEL_PT   ( 7*32+15) /* Intel Processor Trace */
 #define X86_FEATURE_VIRT_SSBD  ( 7*32+16) /* Virtualized Speculative Store Bypass Disable */
 #define X86_FEATURE_ZEN                ( 7*32+17) /* "" CPU is AMD family 0x17 (Zen) */
-#define X86_FEATURE_AMD_SSBD   ( 7*32+18) /* "" AMD RDS implementation */
+#define X86_FEATURE_LS_CFG_SSBD        ( 7*32+18) /* "" AMD SSBD implementation via LS_CFG MSR */
 #define X86_FEATURE_RSB_CTXSW  ( 7*32+19) /* "" Fill RSB on context switches */
 #define X86_FEATURE_IBRS       ( 7*32+20) /* Control Speculation Control */
 #define X86_FEATURE_STIBP      ( 7*32+21) /* Single Thread Indirect Branch Predictors */

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index c86e2196ca1c6ec22ddebdf86319e53d02c86dd8..32945dfce9734db1818d83ef5d2e3afcec6828ab 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -552,7 +552,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
                 */
                if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
                        setup_force_cpu_cap(X86_FEATURE_SSBD);
-                       setup_force_cpu_cap(X86_FEATURE_AMD_SSBD);
+                       setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
                        x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
                }
        }
@@ -804,10 +804,10 @@ static void init_amd(struct cpuinfo_x86 *c)
        /* AMD CPUs don't reset SS attributes on SYSRET */
        set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
 
-       if (boot_cpu_has(X86_FEATURE_AMD_SSBD) ||
+       if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
            cpu_has(c, X86_FEATURE_VIRT_SSBD)) {
                set_cpu_cap(c, X86_FEATURE_SSBD);
-               set_cpu_cap(c, X86_FEATURE_AMD_SSBD);
+               set_cpu_cap(c, X86_FEATURE_LS_CFG_SSBD);
        }
 }
 

diff --git a/arch/x86/kernel/cpu/bugs_64.c b/arch/x86/kernel/cpu/bugs_64.c
index e5251bfc606e4d8f645cadfa01695b79421f438b..d046b49feccb34a322c872b070d2c14c79d33896 100644 (file)
--- a/arch/x86/kernel/cpu/bugs_64.c
+++ b/arch/x86/kernel/cpu/bugs_64.c
@@ -363,7 +363,7 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
         * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
         * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
         */
-       if (!static_cpu_has(X86_FEATURE_AMD_SSBD) &&
+       if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
            !static_cpu_has(X86_FEATURE_VIRT_SSBD))
                return;
 
@@ -397,7 +397,7 @@ static void x86_amd_ssbd_enable(void)
 
        if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
                wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
-       else if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
+       else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
                wrmsrl(MSR_AMD64_LS_CFG, msrval);
 }
 

diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index c6d19f35bb57ed9025cfd4b827fe390957dd5833..cc0133f67f8659c09d28d9c2cf719951b42b2088 100644 (file)
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -360,7 +360,7 @@ static __always_inline void __speculative_store_bypass_update(unsigned long tifn
 {
        if (static_cpu_has(X86_FEATURE_VIRT_SSBD))
                amd_set_ssb_virt_state(tifn);
-       else if (static_cpu_has(X86_FEATURE_AMD_SSBD))
+       else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD))
                amd_set_core_ssb_state(tifn);
        else
                intel_set_ssb_state(tifn);

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 4833ceaf780e3d11d1dcd09f80abbb28ca475c71..894acfa0a7f0a500ec631877eabe97daf0bb7a04 100644 (file)
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -597,7 +597,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
                if ( !boot_cpu_has(X86_FEATURE_IBPB) )
                        entry->ebx &= ~(1u << KVM_CPUID_BIT_IBPB);
 
-               if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
+               if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
                        entry->ebx |= KF(VIRT_SSBD);
                break;
        }