drm/amdgpu/mes12: load unified mes fw on pipe0 and pipe1

Enable unified mes firmware to load on pipe0 and pipe1.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit e69c2dd7534f3fcabf7bb801db2a7ac71e7e5da6)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 8ef53f48ce1506846778263c82151ba7ca61fb9e..81bed8e8478d15bd2a19800c338162a0a0876fef 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -1501,7 +1501,7 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe)
 
        amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix,
                                       sizeof(ucode_prefix));
-       if (adev->enable_uni_mes && pipe == AMDGPU_MES_SCHED_PIPE) {
+       if (adev->enable_uni_mes) {
                snprintf(fw_name, sizeof(fw_name),
                         "amdgpu/%s_uni_mes.bin", ucode_prefix);
        } else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) &&

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index 515de65d8aa0d741041f2439226677a2d609b63c..28bb72d2cffdd4d72efe5dfcea9ed6182d669037 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -744,16 +744,11 @@ static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable)
        if (enable) {
                data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
                data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
-               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,
-                      (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0);
+               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
                WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 
                mutex_lock(&adev->srbm_mutex);
                for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
-                       if ((!adev->enable_mes_kiq || adev->enable_uni_mes) &&
-                           pipe == AMDGPU_MES_KIQ_PIPE)
-                               continue;
-
                        soc21_grbm_select(adev, 3, pipe, 0, 0);
 
                        ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
@@ -767,8 +762,7 @@ static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable)
 
                /* unhalt MES and activate pipe0 */
                data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
-               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,
-                      (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0);
+               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);
                WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 
                if (amdgpu_emu_mode)
@@ -784,8 +778,7 @@ static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable)
                data = REG_SET_FIELD(data, CP_MES_CNTL,
                                     MES_INVALIDATE_ICACHE, 1);
                data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
-               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,
-                      (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0);
+               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
                data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
                WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
        }
@@ -800,10 +793,6 @@ static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev)
 
        mutex_lock(&adev->srbm_mutex);
        for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
-               if ((!adev->enable_mes_kiq || adev->enable_uni_mes) &&
-                   pipe == AMDGPU_MES_KIQ_PIPE)
-                       continue;
-
                /* me=3, queue=0 */
                soc21_grbm_select(adev, 3, pipe, 0, 0);
 
@@ -1525,17 +1514,7 @@ static int mes_v12_0_early_init(void *handle)
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        int pipe, r;
 
-       if (adev->enable_uni_mes) {
-               r = amdgpu_mes_init_microcode(adev, AMDGPU_MES_SCHED_PIPE);
-               if (!r)
-                       return 0;
-
-               adev->enable_uni_mes = false;
-       }
-
        for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
-               if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
-                       continue;
                r = amdgpu_mes_init_microcode(adev, pipe);
                if (r)
                        return r;