arm64: dts: exynos: adjust USB DRD clocks with dtschema in Exynos7

Use the same order of USB 3.0 DRD controller clocks as in Exynos5433.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20220129193646.372481-1-krzysztof.kozlowski@canonical.com

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 3364b09c31583ceeaab96547eb4ffe1237d7f062..e38bb02a21529fc4bb80eb604e69bfb927d92add 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -684,11 +684,10 @@
                        reg = <0x15500000 0x100>;
                        clocks = <&clock_fsys0 ACLK_USBDRD300>,
                               <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
-                              <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
                               <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
+                              <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
                               <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
-                       clock-names = "phy", "ref", "phy_pipe",
-                               "phy_utmi", "itp";
+                       clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp";
                        samsung,pmu-syscon = <&pmu_system_controller>;
                        #phy-cells = <1>;
                };