}
 
        /* register div per output */
-       for (i = WZRD_NUM_OUTPUTS - 1; i >= 0 ; i--) {
+       for (i = nr_outputs - 1; i >= 0 ; i--) {
                const char *clkout_name;
 
-               if (of_property_read_string_index(np, "clock-output-names", i,
-                                                 &clkout_name)) {
-                       dev_err(&pdev->dev,
-                               "clock output name not specified\n");
-                       ret = -EINVAL;
-                       goto err_rm_int_clks;
+               clkout_name = kasprintf(GFP_KERNEL, "%s_out%d", dev_name(&pdev->dev), i);
+               if (!clkout_name) {
+                       ret = -ENOMEM;
+                       goto err_rm_int_clk;
                }
+
                if (!i)
                        clk_wzrd->clkout[i] = clk_wzrd_register_divf
                                (&pdev->dev, clkout_name,
                if (IS_ERR(clk_wzrd->clkout[i])) {
                        int j;
 
-                       for (j = i + 1; j < WZRD_NUM_OUTPUTS; j++)
+                       for (j = i + 1; j < nr_outputs; j++)
                                clk_unregister(clk_wzrd->clkout[j]);
                        dev_err(&pdev->dev,
                                "unable to register divider clock\n");