memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
        i2c.valid = false;
 
-       atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
-
-       i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
-
-
-       for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
-               gpio = &i2c_info->asGPIO_Info[i];
-
-               if (gpio->sucI2cId.ucAccess == id) {
-                       i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
-                       i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
-                       i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
-                       i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
-                       i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
-                       i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
-                       i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
-                       i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
-                       i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
-                       i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
-                       i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
-                       i2c.en_data_mask = (1 << gpio->ucDataEnShift);
-                       i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
-                       i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
-                       i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
-                       i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
-
-                       if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
-                               i2c.hw_capable = true;
-                       else
-                               i2c.hw_capable = false;
-
-                       if (gpio->sucI2cId.ucAccess == 0xa0)
-                               i2c.mm_i2c = true;
-                       else
-                               i2c.mm_i2c = false;
-
-                       i2c.i2c_id = gpio->sucI2cId.ucAccess;
-
-                       i2c.valid = true;
-                       break;
+       if (atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
+               i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
+
+               for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
+                       gpio = &i2c_info->asGPIO_Info[i];
+
+                       if (gpio->sucI2cId.ucAccess == id) {
+                               i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
+                               i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
+                               i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
+                               i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
+                               i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
+                               i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
+                               i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
+                               i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
+                               i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
+                               i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
+                               i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
+                               i2c.en_data_mask = (1 << gpio->ucDataEnShift);
+                               i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
+                               i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
+                               i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
+                               i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
+
+                               if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
+                                       i2c.hw_capable = true;
+                               else
+                                       i2c.hw_capable = false;
+
+                               if (gpio->sucI2cId.ucAccess == 0xa0)
+                                       i2c.mm_i2c = true;
+                               else
+                                       i2c.mm_i2c = false;
+
+                               i2c.i2c_id = gpio->sucI2cId.ucAccess;
+
+                               i2c.valid = true;
+                               break;
+                       }
                }
        }
 
        memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
        gpio.valid = false;
 
-       atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
+       if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
+               gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 
-       gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
+               num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
+                       sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 
-       num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
-
-       for (i = 0; i < num_indices; i++) {
-               pin = &gpio_info->asGPIO_Pin[i];
-               if (id == pin->ucGPIO_ID) {
-                       gpio.id = pin->ucGPIO_ID;
-                       gpio.reg = pin->usGpioPin_AIndex * 4;
-                       gpio.mask = (1 << pin->ucGpioPinBitShift);
-                       gpio.valid = true;
-                       break;
+               for (i = 0; i < num_indices; i++) {
+                       pin = &gpio_info->asGPIO_Pin[i];
+                       if (id == pin->ucGPIO_ID) {
+                               gpio.id = pin->ucGPIO_ID;
+                               gpio.reg = pin->usGpioPin_AIndex * 4;
+                               gpio.mask = (1 << pin->ucGpioPinBitShift);
+                               gpio.valid = true;
+                               break;
+                       }
                }
        }
 
        struct radeon_gpio_rec gpio;
        struct radeon_hpd hpd;
 
-       atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
-
-       if (data_offset == 0)
+       if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
                return false;
 
        if (crev < 2)
                                    GetIndexIntoMasterTable(DATA,
                                                            IntegratedSystemInfo);
 
-                               atom_parse_data_header(ctx, index, &size, &frev,
-                                                      &crev, &igp_offset);
-
-                               if (crev >= 2) {
-                                       igp_obj =
-                                           (ATOM_INTEGRATED_SYSTEM_INFO_V2
-                                            *) (ctx->bios + igp_offset);
-
-                                       if (igp_obj) {
-                                               uint32_t slot_config, ct;
-
-                                               if (con_obj_num == 1)
-                                                       slot_config =
-                                                           igp_obj->
-                                                           ulDDISlot1Config;
-                                               else
-                                                       slot_config =
-                                                           igp_obj->
-                                                           ulDDISlot2Config;
-
-                                               ct = (slot_config >> 16) & 0xff;
-                                               connector_type =
-                                                   object_connector_convert
-                                                   [ct];
-                                               connector_object_id = ct;
-                                               igp_lane_info =
-                                                   slot_config & 0xffff;
+                               if (atom_parse_data_header(ctx, index, &size, &frev,
+                                                          &crev, &igp_offset)) {
+
+                                       if (crev >= 2) {
+                                               igp_obj =
+                                                       (ATOM_INTEGRATED_SYSTEM_INFO_V2
+                                                        *) (ctx->bios + igp_offset);
+
+                                               if (igp_obj) {
+                                                       uint32_t slot_config, ct;
+
+                                                       if (con_obj_num == 1)
+                                                               slot_config =
+                                                                       igp_obj->
+                                                                       ulDDISlot1Config;
+                                                       else
+                                                               slot_config =
+                                                                       igp_obj->
+                                                                       ulDDISlot2Config;
+
+                                                       ct = (slot_config >> 16) & 0xff;
+                                                       connector_type =
+                                                               object_connector_convert
+                                                               [ct];
+                                                       connector_object_id = ct;
+                                                       igp_lane_info =
+                                                               slot_config & 0xffff;
+                                               } else
+                                                       continue;
                                        } else
                                                continue;
-                               } else
-                                       continue;
+                               } else {
+                                       igp_lane_info = 0;
+                                       connector_type =
+                                               object_connector_convert[con_obj_id];
+                                       connector_object_id = con_obj_id;
+                               }
                        } else {
                                igp_lane_info = 0;
                                connector_type =
                uint8_t frev, crev;
                ATOM_XTMDS_INFO *xtmds;
 
-               atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
-               xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
+               if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
+                       xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 
-               if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
-                       if (connector_type == DRM_MODE_CONNECTOR_DVII)
-                               return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
-                       else
-                               return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
-               } else {
-                       if (connector_type == DRM_MODE_CONNECTOR_DVII)
-                               return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
-                       else
-                               return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
-               }
+                       if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
+                               if (connector_type == DRM_MODE_CONNECTOR_DVII)
+                                       return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
+                               else
+                                       return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
+                       } else {
+                               if (connector_type == DRM_MODE_CONNECTOR_DVII)
+                                       return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
+                               else
+                                       return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
+                       }
+               } else
+                       return supported_devices_connector_object_id_convert
+                               [connector_type];
        } else {
                return supported_devices_connector_object_id_convert
                        [connector_type];
        int i, j, max_device;
        struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
 
-       atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
+       if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
+               return false;
 
        supported_devices =
            (union atom_supported_devices *)(ctx->bios + data_offset);
        struct radeon_pll *mpll = &rdev->clock.mpll;
        uint16_t data_offset;
 
-       atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
-                              &crev, &data_offset);
-
-       firmware_info =
-           (union firmware_info *)(mode_info->atom_context->bios +
-                                   data_offset);
-
-       if (firmware_info) {
+       if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                  &frev, &crev, &data_offset)) {
+               firmware_info =
+                       (union firmware_info *)(mode_info->atom_context->bios +
+                                               data_offset);
                /* pixel clocks */
                p1pll->reference_freq =
                    le16_to_cpu(firmware_info->info.usReferenceClock);
        u8 frev, crev;
        u16 data_offset;
 
-       atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
-                              &crev, &data_offset);
-
-       igp_info = (union igp_info *)(mode_info->atom_context->bios +
+       if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                  &frev, &crev, &data_offset)) {
+               igp_info = (union igp_info *)(mode_info->atom_context->bios +
                                      data_offset);
-
-       if (igp_info) {
                switch (crev) {
                case 1:
                        if (igp_info->info.ucMemoryType & 0xf0)
        uint16_t maxfreq;
        int i;
 
-       atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
-                              &crev, &data_offset);
+       if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                  &frev, &crev, &data_offset)) {
+               tmds_info =
+                       (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
+                                                  data_offset);
 
-       tmds_info =
-           (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
-                                      data_offset);
-
-       if (tmds_info) {
                maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
                for (i = 0; i < 4; i++) {
                        tmds->tmds_pll[i].freq =
        if (id > ATOM_MAX_SS_ENTRY)
                return NULL;
 
-       atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
-                              &crev, &data_offset);
-
-       ss_info =
-           (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
+       if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                  &frev, &crev, &data_offset)) {
+               ss_info =
+                       (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
 
-       if (ss_info) {
                ss =
                    kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
 
        uint8_t frev, crev;
        struct radeon_encoder_atom_dig *lvds = NULL;
 
-       atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
-                              &crev, &data_offset);
-
-       lvds_info =
-           (union lvds_info *)(mode_info->atom_context->bios + data_offset);
-
-       if (lvds_info) {
+       if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                  &frev, &crev, &data_offset)) {
+               lvds_info =
+                       (union lvds_info *)(mode_info->atom_context->bios + data_offset);
                lvds =
                    kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
 
        uint8_t bg, dac;
        struct radeon_encoder_primary_dac *p_dac = NULL;
 
-       atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
+       if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                  &frev, &crev, &data_offset)) {
+               dac_info = (struct _COMPASSIONATE_DATA *)
+                       (mode_info->atom_context->bios + data_offset);
 
-       dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
-
-       if (dac_info) {
                p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
 
                if (!p_dac)
        u8 frev, crev;
        u16 data_offset, misc;
 
-       atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
+       if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
+                                   &frev, &crev, &data_offset))
+               return false;
 
        switch (crev) {
        case 1:
        struct _ATOM_ANALOG_TV_INFO *tv_info;
        enum radeon_tv_std tv_std = TV_STD_NTSC;
 
-       atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
+       if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                  &frev, &crev, &data_offset)) {
 
-       tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
+               tv_info = (struct _ATOM_ANALOG_TV_INFO *)
+                       (mode_info->atom_context->bios + data_offset);
 
-       switch (tv_info->ucTV_BootUpDefaultStandard) {
-       case ATOM_TV_NTSC:
-               tv_std = TV_STD_NTSC;
-               DRM_INFO("Default TV standard: NTSC\n");
-               break;
-       case ATOM_TV_NTSCJ:
-               tv_std = TV_STD_NTSC_J;
-               DRM_INFO("Default TV standard: NTSC-J\n");
-               break;
-       case ATOM_TV_PAL:
-               tv_std = TV_STD_PAL;
-               DRM_INFO("Default TV standard: PAL\n");
-               break;
-       case ATOM_TV_PALM:
-               tv_std = TV_STD_PAL_M;
-               DRM_INFO("Default TV standard: PAL-M\n");
-               break;
-       case ATOM_TV_PALN:
-               tv_std = TV_STD_PAL_N;
-               DRM_INFO("Default TV standard: PAL-N\n");
-               break;
-       case ATOM_TV_PALCN:
-               tv_std = TV_STD_PAL_CN;
-               DRM_INFO("Default TV standard: PAL-CN\n");
-               break;
-       case ATOM_TV_PAL60:
-               tv_std = TV_STD_PAL_60;
-               DRM_INFO("Default TV standard: PAL-60\n");
-               break;
-       case ATOM_TV_SECAM:
-               tv_std = TV_STD_SECAM;
-               DRM_INFO("Default TV standard: SECAM\n");
-               break;
-       default:
-               tv_std = TV_STD_NTSC;
-               DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
-               break;
+               switch (tv_info->ucTV_BootUpDefaultStandard) {
+               case ATOM_TV_NTSC:
+                       tv_std = TV_STD_NTSC;
+                       DRM_INFO("Default TV standard: NTSC\n");
+                       break;
+               case ATOM_TV_NTSCJ:
+                       tv_std = TV_STD_NTSC_J;
+                       DRM_INFO("Default TV standard: NTSC-J\n");
+                       break;
+               case ATOM_TV_PAL:
+                       tv_std = TV_STD_PAL;
+                       DRM_INFO("Default TV standard: PAL\n");
+                       break;
+               case ATOM_TV_PALM:
+                       tv_std = TV_STD_PAL_M;
+                       DRM_INFO("Default TV standard: PAL-M\n");
+                       break;
+               case ATOM_TV_PALN:
+                       tv_std = TV_STD_PAL_N;
+                       DRM_INFO("Default TV standard: PAL-N\n");
+                       break;
+               case ATOM_TV_PALCN:
+                       tv_std = TV_STD_PAL_CN;
+                       DRM_INFO("Default TV standard: PAL-CN\n");
+                       break;
+               case ATOM_TV_PAL60:
+                       tv_std = TV_STD_PAL_60;
+                       DRM_INFO("Default TV standard: PAL-60\n");
+                       break;
+               case ATOM_TV_SECAM:
+                       tv_std = TV_STD_SECAM;
+                       DRM_INFO("Default TV standard: SECAM\n");
+                       break;
+               default:
+                       tv_std = TV_STD_NTSC;
+                       DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
+                       break;
+               }
        }
        return tv_std;
 }
        uint8_t bg, dac;
        struct radeon_encoder_tv_dac *tv_dac = NULL;
 
-       atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
+       if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                  &frev, &crev, &data_offset)) {
 
-       dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
+               dac_info = (struct _COMPASSIONATE_DATA *)
+                       (mode_info->atom_context->bios + data_offset);
 
-       if (dac_info) {
                tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
 
                if (!tv_dac)
        int state_index = 0, mode_index = 0;
        struct radeon_i2c_bus_rec i2c_bus;
 
-       atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
-
-       power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
-
        rdev->pm.default_power_state = NULL;
 
-       if (power_info) {
+       if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                  &frev, &crev, &data_offset)) {
+               power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
                if (frev < 4) {
                        /* add the i2c bus for thermal/fan chip */
                        if (power_info->info.ucOverdriveThermalController > 0) {
 
        }
 }
 
+union igp_info {
+       struct _ATOM_INTEGRATED_SYSTEM_INFO info;
+       struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
+};
+
 void rs690_pm_info(struct radeon_device *rdev)
 {
        int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
-       struct _ATOM_INTEGRATED_SYSTEM_INFO *info;
-       struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2;
-       void *ptr;
+       union igp_info *info;
        uint16_t data_offset;
        uint8_t frev, crev;
        fixed20_12 tmp;
 
-       atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
-                              &frev, &crev, &data_offset);
-       ptr = rdev->mode_info.atom_context->bios + data_offset;
-       info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr;
-       info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr;
-       /* Get various system informations from bios */
-       switch (crev) {
-       case 1:
-               tmp.full = rfixed_const(100);
-               rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock);
-               rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
-               rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock));
-               rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock));
-               rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth);
-               break;
-       case 2:
-               tmp.full = rfixed_const(100);
-               rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock);
-               rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
-               rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock);
-               rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
-               rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq);
-               rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
-               rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth));
-               break;
-       default:
+       if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
+                                  &frev, &crev, &data_offset)) {
+               info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
+
+               /* Get various system informations from bios */
+               switch (crev) {
+               case 1:
+                       tmp.full = rfixed_const(100);
+                       rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info.ulBootUpMemoryClock);
+                       rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
+                       rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
+                       rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->info.usFSBClock));
+                       rdev->pm.igp_ht_link_width.full = rfixed_const(info->info.ucHTLinkWidth);
+                       break;
+               case 2:
+                       tmp.full = rfixed_const(100);
+                       rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info_v2.ulBootUpSidePortClock);
+                       rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
+                       rdev->pm.igp_system_mclk.full = rfixed_const(info->info_v2.ulBootUpUMAClock);
+                       rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
+                       rdev->pm.igp_ht_link_clk.full = rfixed_const(info->info_v2.ulHTLinkFreq);
+                       rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
+                       rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
+                       break;
+               default:
+                       tmp.full = rfixed_const(100);
+                       /* We assume the slower possible clock ie worst case */
+                       /* DDR 333Mhz */
+                       rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
+                       /* FIXME: system clock ? */
+                       rdev->pm.igp_system_mclk.full = rfixed_const(100);
+                       rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
+                       rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
+                       rdev->pm.igp_ht_link_width.full = rfixed_const(8);
+                       DRM_ERROR("No integrated system info for your GPU, using safe default\n");
+                       break;
+               }
+       } else {
                tmp.full = rfixed_const(100);
                /* We assume the slower possible clock ie worst case */
                /* DDR 333Mhz */
                rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
                rdev->pm.igp_ht_link_width.full = rfixed_const(8);
                DRM_ERROR("No integrated system info for your GPU, using safe default\n");
-               break;
        }
        /* Compute various bandwidth */
        /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4  */