KVM: arm64: Constraint PAuth support to consistent implementations

PAuth comes it two parts: address authentication, and generic
authentication. So far, KVM mandates that both are implemented.

PAuth also comes in three flavours: Q5, Q3, and IMPDEF. Only one
can be implemented for any of address and generic authentication.

Crucially, the architecture doesn't mandate that address and generic
authentication implement the *same* flavour. This would make
implementing ERETAx very difficult for NV, something we are not
terribly keen on.

So only allow PAuth support for KVM on systems that are not totally
insane. Which is so far 100% of the known HW.

Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240419102935.1935571-4-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index c4a0a35e02c72866b87c8a3e827b87ed5303504e..d32ffbfef724350f0c29d9a6a6968ff16a74248b 100644 (file)
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -218,6 +218,40 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
        kvm_arm_teardown_hypercalls(kvm);
 }
 
+static bool kvm_has_full_ptr_auth(void)
+{
+       bool apa, gpa, api, gpi, apa3, gpa3;
+       u64 isar1, isar2, val;
+
+       /*
+        * Check that:
+        *
+        * - both Address and Generic auth are implemented for a given
+         *   algorithm (Q5, IMPDEF or Q3)
+        * - only a single algorithm is implemented.
+        */
+       if (!system_has_full_ptr_auth())
+               return false;
+
+       isar1 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR1_EL1);
+       isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);
+
+       apa = !!FIELD_GET(ID_AA64ISAR1_EL1_APA_MASK, isar1);
+       val = FIELD_GET(ID_AA64ISAR1_EL1_GPA_MASK, isar1);
+       gpa = (val == ID_AA64ISAR1_EL1_GPA_IMP);
+
+       api = !!FIELD_GET(ID_AA64ISAR1_EL1_API_MASK, isar1);
+       val = FIELD_GET(ID_AA64ISAR1_EL1_GPI_MASK, isar1);
+       gpi = (val == ID_AA64ISAR1_EL1_GPI_IMP);
+
+       apa3 = !!FIELD_GET(ID_AA64ISAR2_EL1_APA3_MASK, isar2);
+       val  = FIELD_GET(ID_AA64ISAR2_EL1_GPA3_MASK, isar2);
+       gpa3 = (val == ID_AA64ISAR2_EL1_GPA3_IMP);
+
+       return (apa == gpa && api == gpi && apa3 == gpa3 &&
+               (apa + api + apa3) == 1);
+}
+
 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 {
        int r;
@@ -311,7 +345,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
                break;
        case KVM_CAP_ARM_PTRAUTH_ADDRESS:
        case KVM_CAP_ARM_PTRAUTH_GENERIC:
-               r = system_has_full_ptr_auth();
+               r = kvm_has_full_ptr_auth();
                break;
        case KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE:
                if (kvm)
@@ -1270,7 +1304,7 @@ static unsigned long system_supported_vcpu_features(void)
        if (!system_supports_sve())
                clear_bit(KVM_ARM_VCPU_SVE, &features);
 
-       if (!system_has_full_ptr_auth()) {
+       if (!kvm_has_full_ptr_auth()) {
                clear_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, &features);
                clear_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, &features);
        }