status = "disabled";
        };
 
+       gpmc0: memory-controller@3b000000 {
+               compatible = "ti,am64-gpmc";
+               power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 80 0>;
+               clock-names = "fck";
+               reg = <0x00 0x03b000000 0x00 0x400>,
+                     <0x00 0x050000000 0x00 0x8000000>;
+               reg-names = "cfg", "data";
+               interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+               gpmc,num-cs = <3>;
+               gpmc,num-waitpins = <2>;
+               #address-cells = <2>;
+               #size-cells = <1>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               status = "disabled";
+       };
+
+       elm0: ecc@25010000 {
+               compatible = "ti,am64-elm";
+               reg = <0x00 0x25010000 0x00 0x2000>;
+               interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 54 0>;
+               clock-names = "fck";
+               status = "disabled";
+       };
 };
 
                         <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
                         <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
                         <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
+                        <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
                         <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
                         <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
                         <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
                         <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
                         <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
+                        <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
                         <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
                         <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
                         <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */