net: axienet: Fix register defines comment description

In axiethernet header fix register defines comment description to be
inline with IP documentation. It updates MAC configuration register,
MDIO configuration register and frame filter control description.

Fixes: 8a3b7a252dca ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
index fa5500decc9602c38ccf930cb6983a401f5b9c1f..c7d9221fafdcb1af0fc9d483177043f936fed626 100644 (file)
--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
@@ -160,16 +160,16 @@
 #define XAE_RCW1_OFFSET                0x00000404 /* Rx Configuration Word 1 */
 #define XAE_TC_OFFSET          0x00000408 /* Tx Configuration */
 #define XAE_FCC_OFFSET         0x0000040C /* Flow Control Configuration */
-#define XAE_EMMC_OFFSET                0x00000410 /* EMAC mode configuration */
-#define XAE_PHYC_OFFSET                0x00000414 /* RGMII/SGMII configuration */
+#define XAE_EMMC_OFFSET                0x00000410 /* MAC speed configuration */
+#define XAE_PHYC_OFFSET                0x00000414 /* RX Max Frame Configuration */
 #define XAE_ID_OFFSET          0x000004F8 /* Identification register */
-#define XAE_MDIO_MC_OFFSET     0x00000500 /* MII Management Config */
-#define XAE_MDIO_MCR_OFFSET    0x00000504 /* MII Management Control */
-#define XAE_MDIO_MWD_OFFSET    0x00000508 /* MII Management Write Data */
-#define XAE_MDIO_MRD_OFFSET    0x0000050C /* MII Management Read Data */
+#define XAE_MDIO_MC_OFFSET     0x00000500 /* MDIO Setup */
+#define XAE_MDIO_MCR_OFFSET    0x00000504 /* MDIO Control */
+#define XAE_MDIO_MWD_OFFSET    0x00000508 /* MDIO Write Data */
+#define XAE_MDIO_MRD_OFFSET    0x0000050C /* MDIO Read Data */
 #define XAE_UAW0_OFFSET                0x00000700 /* Unicast address word 0 */
 #define XAE_UAW1_OFFSET                0x00000704 /* Unicast address word 1 */
-#define XAE_FMI_OFFSET         0x00000708 /* Filter Mask Index */
+#define XAE_FMI_OFFSET         0x00000708 /* Frame Filter Control */
 #define XAE_AF0_OFFSET         0x00000710 /* Address Filter 0 */
 #define XAE_AF1_OFFSET         0x00000714 /* Address Filter 1 */
 
@@ -308,7 +308,7 @@
  */
 #define XAE_UAW1_UNICASTADDR_MASK      0x0000FFFF
 
-/* Bit masks for Axi Ethernet FMI register */
+/* Bit masks for Axi Ethernet FMC register */
 #define XAE_FMI_PM_MASK                        0x80000000 /* Promis. mode enable */
 #define XAE_FMI_IND_MASK               0x00000003 /* Index Mask */