drm/i915: Parsing the PWM cntrl and CABC ON/OFF fields in VBT

For dual link panel scenarios there are new fields added in the
VBT which indicate on which port the PWM cntrl and CABC ON/OFF
commands needs to be sent.

v2: Moving the comment to intel_dsi.h(Jani)

v3: Renaming the field names (Jani)

v4 by Jani: make this patch only about VBT

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Yetunde Adebisi <yetundex.adebisi@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1459346623-30752-2-git-send-email-jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index e72dd9a8d6bf41e9f089eb76643fb5e7ff7a8922..dbbd591717222dc619ace63f6fe5a77ec0a369c5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -763,6 +763,16 @@ parse_mipi_config(struct drm_i915_private *dev_priv,
                return;
        }
 
+       /*
+        * These fields are introduced from the VBT version 197 onwards,
+        * so making sure that these bits are set zero in the previous
+        * versions.
+        */
+       if (dev_priv->vbt.dsi.config->dual_link && bdb->version < 197) {
+               dev_priv->vbt.dsi.config->dl_dcs_cabc_ports = 0;
+               dev_priv->vbt.dsi.config->dl_dcs_backlight_ports = 0;
+       }
+
        /* We have mandatory mipi config blocks. Initialize as generic panel */
        dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
 }

diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index ab0ea315eddb1665a96b78fbde53d72e004c1773..149c3226e895e569c7a38cb1cc7e3708deb844b8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -113,7 +113,13 @@ struct mipi_config {
        u16 dual_link:2;
        u16 lane_cnt:2;
        u16 pixel_overlap:3;
-       u16 rsvd3:9;
+       u16 rgb_flip:1;
+#define DL_DCS_PORT_A                  0x00
+#define DL_DCS_PORT_C                  0x01
+#define DL_DCS_PORT_A_AND_C            0x02
+       u16 dl_dcs_cabc_ports:2;
+       u16 dl_dcs_backlight_ports:2;
+       u16 rsvd3:4;
 
        u16 rsvd4;