arm64: dts: qcom: sm8550: Add graphics clock controller

Add device node for graphics clock controller on Qualcomm
SM8550 platform.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524181800.28717-4-quic_jkona@quicinc.com

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 29b99003d8a9f99508b702f3110bd883864f95c8..20924d570c07e8b42b1e0e82585154f791e6915b 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
+#include <dt-bindings/clock/qcom,sm8550-gpucc.h>
 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
 #include <dt-bindings/dma/qcom-gpi.h>
@@ -1952,6 +1953,17 @@
                        #reset-cells = <1>;
                };
 
+               gpucc: clock-controller@3d90000 {
+                       compatible = "qcom,sm8550-gpucc";
+                       reg = <0 0x03d90000 0 0xa000>;
+                       clocks = <&bi_tcxo_div2>,
+                                <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+                                <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                remoteproc_mpss: remoteproc@4080000 {
                        compatible = "qcom,sm8550-mpss-pas";
                        reg = <0x0 0x04080000 0x0 0x4040>;