target/mips: Make cpu_HI/LO registers public

We will access the cpu_HI/LO registers outside of translate.c.
Make them publicly accessible.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-4-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

diff --git a/target/mips/translate.c b/target/mips/translate.c
index a6e835809aaf732606eeccffd05ef0e817818e13..c20f630b7e7fc9dbc1901fe6c74eafa64b521127 100644 (file)
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2179,7 +2179,7 @@ enum {
 
 /* global register indices */
 TCGv cpu_gpr[32], cpu_PC;
-static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
+TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
 static TCGv cpu_dspctrl, btarget;
 TCGv bcond;
 static TCGv cpu_lladdr, cpu_llval;

diff --git a/target/mips/translate.h b/target/mips/translate.h
index f47b5f2c8d06f70beec576a6fd36488f5fa19df7..2a1d8f570bb1bedaa89fc09d07588c9affd5380f 100644 (file)
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -145,6 +145,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 
 extern TCGv cpu_gpr[32], cpu_PC;
+extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
 extern TCGv_i32 fpu_fcr0, fpu_fcr31;
 extern TCGv_i64 fpu_f64[32];
 extern TCGv bcond;