return mode;
 }
 
+static unsigned int __init get_extal_freq(void)
+{
+       struct device_node *cpg, *extal;
+       u32 freq = 20000000;
+
+       cpg = of_find_compatible_node(NULL, NULL,
+                                     "renesas,rcar-gen2-cpg-clocks");
+       if (!cpg)
+               return freq;
+
+       extal = of_parse_phandle(cpg, "clocks", 0);
+       of_node_put(cpg);
+       if (!extal)
+               return freq;
+
+       of_property_read_u32(extal, "clock-frequency", &freq);
+       of_node_put(extal);
+       return freq;
+}
+
 #define CNTCR 0
 #define CNTFID0 0x20
 
        u32 mode = rcar_gen2_read_mode_pins();
 #ifdef CONFIG_ARM_ARCH_TIMER
        void __iomem *base;
-       int extal_mhz = 0;
        u32 freq;
 
        if (of_machine_is_compatible("renesas,r8a7794")) {
                 * with the counter disabled. Moreover, it may also report
                 * a potentially incorrect fixed 13 MHz frequency. To be
                 * correct these registers need to be updated to use the
-                * frequency EXTAL / 2 which can be determined by the MD pins.
+                * frequency EXTAL / 2.
                 */
-
-               switch (mode & (MD(14) | MD(13))) {
-               case 0:
-                       extal_mhz = 15;
-                       break;
-               case MD(13):
-                       extal_mhz = 20;
-                       break;
-               case MD(14):
-                       extal_mhz = 26;
-                       break;
-               case MD(13) | MD(14):
-                       extal_mhz = 30;
-                       break;
-               }
-
-               /* The arch timer frequency equals EXTAL / 2 */
-               freq = extal_mhz * (1000000 / 2);
+               freq = get_extal_freq() / 2;
        }
 
        /* Remap "armgcnt address map" space */