struct amdgpu_ring **out_ring);
  void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
  bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
+ int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
  int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
                                     uint32_t flags);
 +bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
  struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
  bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
                                  unsigned long end);
 
                                        unsigned vm_id, uint64_t pd_addr)
  {
        int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
 +      uint32_t seq = ring->fence_drv.sync_seq;
 +      uint64_t addr = ring->fence_drv.gpu_addr;
 +
 +      amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 +      amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
 +                               WAIT_REG_MEM_FUNCTION(3) | /* equal */
 +                               WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
 +      amdgpu_ring_write(ring, addr & 0xfffffffc);
 +      amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 +      amdgpu_ring_write(ring, seq);
 +      amdgpu_ring_write(ring, 0xffffffff);
 +      amdgpu_ring_write(ring, 4); /* poll interval */
  
-       if (usepfp) {
-               /* synce CE with ME to prevent CE fetch CEIB before context switch done */
-               amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
-               amdgpu_ring_write(ring, 0);
-               amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
-               amdgpu_ring_write(ring, 0);
-       }
- 
        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
        amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
                                 WRITE_DATA_DST_SEL(0)));