return rxdesc;
 }
 
-static void dw_spi_dma_setup(struct dw_spi *dws)
+static int mid_spi_dma_setup(struct dw_spi *dws)
 {
        u16 dma_ctrl = 0;
 
-       spi_enable_chip(dws, 0);
-
        dw_writew(dws, DW_SPI_DMARDLR, 0xf);
        dw_writew(dws, DW_SPI_DMATDLR, 0x10);
 
                dma_ctrl |= SPI_DMA_RDMAE;
        dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
 
-       spi_enable_chip(dws, 1);
+       return 0;
 }
 
-static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
+static int mid_spi_dma_transfer(struct dw_spi *dws)
 {
        struct dma_async_tx_descriptor *txdesc, *rxdesc;
 
-       /* 1. setup DMA related registers */
-       if (cs_change)
-               dw_spi_dma_setup(dws);
-
-       /* 2. Prepare the TX dma transfer */
+       /* Prepare the TX dma transfer */
        txdesc = dw_spi_dma_prepare_tx(dws);
 
-       /* 3. Prepare the RX dma transfer */
+       /* Prepare the RX dma transfer */
        rxdesc = dw_spi_dma_prepare_rx(dws);
 
        /* rx must be started before tx due to spi instinct */
 static struct dw_spi_dma_ops mid_dma_ops = {
        .dma_init       = mid_spi_dma_init,
        .dma_exit       = mid_spi_dma_exit,
+       .dma_setup      = mid_spi_dma_setup,
        .dma_transfer   = mid_spi_dma_transfer,
 };
 #endif
 
        struct dw_spi *dws = spi_master_get_devdata(master);
        struct chip_data *chip = spi_get_ctldata(spi);
        u8 imask = 0;
-       u8 cs_change = 0;
        u16 txlevel = 0;
        u16 clk_div = 0;
        u32 speed = 0;
        u32 cr0 = 0;
+       int ret;
 
        dws->n_bytes = chip->n_bytes;
        dws->dma_width = chip->dma_width;
        dws->rx = transfer->rx_buf;
        dws->rx_end = dws->rx + transfer->len;
        dws->len = transfer->len;
-       if (chip != dws->prev_chip)
-               cs_change = 1;
 
        spi_enable_chip(dws, 0);
 
         * Interrupt mode
         * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
         */
-       if (!dws->dma_mapped && !chip->poll_mode) {
+       if (dws->dma_mapped) {
+               ret = dws->dma_ops->dma_setup(dws);
+               if (ret < 0) {
+                       spi_enable_chip(dws, 1);
+                       return ret;
+               }
+       } else if (!chip->poll_mode) {
                txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
                dw_writew(dws, DW_SPI_TXFLTR, txlevel);
 
 
        spi_enable_chip(dws, 1);
 
-       if (cs_change)
-               dws->prev_chip = chip;
-
-       if (dws->dma_mapped)
-               dws->dma_ops->dma_transfer(dws, cs_change);
+       if (dws->dma_mapped) {
+               ret = dws->dma_ops->dma_transfer(dws);
+               if (ret < 0)
+                       return ret;
+       }
 
        if (chip->poll_mode)
                return poll_transfer(dws);
 
        dws->master = master;
        dws->type = SSI_MOTO_SPI;
-       dws->prev_chip = NULL;
        dws->dma_inited = 0;
        dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
        snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
 
 struct dw_spi_dma_ops {
        int (*dma_init)(struct dw_spi *dws);
        void (*dma_exit)(struct dw_spi *dws);
-       int (*dma_transfer)(struct dw_spi *dws, int cs_change);
+       int (*dma_setup)(struct dw_spi *dws);
+       int (*dma_transfer)(struct dw_spi *dws);
 };
 
 struct dw_spi {
        u16                     num_cs;         /* supported slave numbers */
 
        /* Current message transfer state info */
-       struct chip_data        *prev_chip;
        size_t                  len;
        void                    *tx;
        void                    *tx_end;