select HAVE_GENERIC_HARDIRQS
        select GENERIC_IRQ_SHOW
        select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS
+       select GENERIC_CPU_DEVICES
 
 config RWSEM_GENERIC_SPINLOCK
        bool
 
        select HAVE_IDE
        select HAVE_GENERIC_HARDIRQS
        select GENERIC_IRQ_SHOW
+       select GENERIC_CPU_DEVICES
        help
          Xtensa processors are 32-bit RISC machines designed by Tensilica
          primarily for embedded systems.  These processors are both
 
 #include <linux/device.h>
 #include <linux/node.h>
 #include <linux/gfp.h>
+#include <linux/percpu.h>
 
 #include "base.h"
 
 }
 EXPORT_SYMBOL_GPL(cpu_is_hotpluggable);
 
+#ifdef CONFIG_GENERIC_CPU_DEVICES
+static DEFINE_PER_CPU(struct cpu, cpu_devices);
+#endif
+
+static void __init cpu_dev_register_generic(void)
+{
+#ifdef CONFIG_GENERIC_CPU_DEVICES
+       int i;
+
+       for_each_possible_cpu(i) {
+               if (register_cpu(&per_cpu(cpu_devices, i), i))
+                       panic("Failed to register CPU device");
+       }
+#endif
+}
+
 void __init cpu_dev_init(void)
 {
        if (subsys_system_register(&cpu_subsys, cpu_root_attr_groups))
                panic("Failed to register CPU subsystem");
 
+       cpu_dev_register_generic();
+
 #if defined(CONFIG_SCHED_MC) || defined(CONFIG_SCHED_SMT)
        sched_create_sysfs_power_savings_entries(cpu_subsys.dev_root);
 #endif