drm/amdgpu remove restriction of sriov max_pfn on Vega10

Remove restriction of sriov max_pfn so that TBA and TMA can move to high
47 bits address.

Regression test: change range alloc flag of libdrm as
AMDGPU_VA_RANGE_HIGH and there is no flr occur when testing amdgpu_test
of drm.

Signed-off-by: Lin.Cao <lincao12@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 5fed01e34928253a6b58a6ca5785900d41e710cf..fee3141bb607b0f84faef737f85e2e359a174b41 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -2018,11 +2018,8 @@ static int gmc_v9_0_sw_init(void *handle)
                 * vm size is 256TB (48bit), maximum size of Vega10,
                 * block size 512 (9bit)
                 */
-               /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
-               if (amdgpu_sriov_vf(adev))
-                       amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
-               else
-                       amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
+
+               amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
                if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2))
                        adev->gmc.translate_further = adev->vm_manager.num_level > 1;
                break;