drm/amd/powerplay: add is_dpm_running for SMU11

add is_dpm_running function to support smu s3 case.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 00ef6f1c9d30920664c0e174a229165b59ccc4ad..d2adacc6a7c044c0b39b34a163909fe074f91b57 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -483,6 +483,7 @@ struct smu_funcs
        int (*init_display)(struct smu_context *smu);
        int (*set_allowed_mask)(struct smu_context *smu);
        int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
+       bool (*is_dpm_running)(struct smu_context *smu);
        int (*enable_all_mask)(struct smu_context *smu);
        int (*disable_all_mask)(struct smu_context *smu);
        int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
@@ -608,6 +609,8 @@ struct smu_funcs
        ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
 #define smu_feature_get_enabled_mask(smu, mask, num) \
        ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
+#define smu_is_dpm_running(smu) \
+       ((smu)->funcs->is_dpm_running ? (smu)->funcs->is_dpm_running((smu)) : 0)
 #define smu_feature_enable_all(smu) \
        ((smu)->funcs->enable_all_mask? (smu)->funcs->enable_all_mask((smu)) : 0)
 #define smu_feature_disable_all(smu) \

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 21490867f40ff46ec6ff605e0fa86022d11ffcff..9fe34c4a16f6a497ab9d33a059a8eceeb8cc2d10 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -50,6 +50,16 @@ MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
 #define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
 #define SMU11_VOLTAGE_SCALE 4
 
+#define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
+                        FEATURE_DPM_GFXCLK_MASK | \
+                        FEATURE_DPM_UCLK_MASK | \
+                        FEATURE_DPM_SOCCLK_MASK | \
+                        FEATURE_DPM_UVD_MASK | \
+                        FEATURE_DPM_VCE_MASK | \
+                        FEATURE_DPM_MP0CLK_MASK | \
+                        FEATURE_DPM_LINK_MASK | \
+                        FEATURE_DPM_DCEFCLK_MASK)
+
 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
                                              uint16_t msg)
 {
@@ -750,6 +760,17 @@ static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
        return ret;
 }
 
+static bool smu_v11_0_is_dpm_running(struct smu_context *smu)
+{
+       int ret = 0;
+       uint32_t feature_mask[2];
+       unsigned long feature_enabled;
+       ret = smu_v11_0_get_enabled_mask(smu, feature_mask, 2);
+       feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
+                          ((uint64_t)feature_mask[1] << 32));
+       return !!(feature_enabled & SMC_DPM_FEATURE);
+}
+
 static int smu_v11_0_enable_all_mask(struct smu_context *smu)
 {
        struct smu_feature *feature = &smu->smu_feature;
@@ -1962,6 +1983,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
        .init_display = smu_v11_0_init_display,
        .set_allowed_mask = smu_v11_0_set_allowed_mask,
        .get_enabled_mask = smu_v11_0_get_enabled_mask,
+       .is_dpm_running = smu_v11_0_is_dpm_running,
        .enable_all_mask = smu_v11_0_enable_all_mask,
        .disable_all_mask = smu_v11_0_disable_all_mask,
        .update_feature_enable_state = smu_v11_0_update_feature_enable_state,