drm/i915: add support for power wells

This defines the registers used by different power wells.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 908550c72a0d49952165bede651c649281774354..61ee4142d643179cef809de763e9f5d95052c962 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4021,4 +4021,17 @@
 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI          (0xf << 16)
 #define   AUD_CONFIG_DISABLE_NCTS              (1 << 3)
 
+/* HSW Power Wells */
+#define HSW_PWR_WELL_CTL1              0x45400         /* BIOS */
+#define HSW_PWR_WELL_CTL2              0x45404         /* Driver */
+#define HSW_PWR_WELL_CTL3              0x45408         /* KVMR */
+#define HSW_PWR_WELL_CTL4              0x4540C         /* Debug */
+#define   HSW_PWR_WELL_ENABLE                          (1<<31)
+#define   HSW_PWR_WELL_STATE                           (1<<30)
+#define HSW_PWR_WELL_CTL5              0x45410
+#define   HSW_PWR_WELL_ENABLE_SINGLE_STEP      (1<<31)
+#define   HSW_PWR_WELL_PWR_GATE_OVERRIDE       (1<<20)
+#define   HSW_PWR_WELL_FORCE_ON                                (1<<19)
+#define HSW_PWR_WELL_CTL6              0x45414
+
 #endif /* _I915_REG_H_ */