return 0;
 }
 
-static void mes_v11_0_kiq_dequeue_sched(struct amdgpu_device *adev)
+static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring)
 {
        uint32_t data;
        int i;
+       struct amdgpu_device *adev = ring->adev;
 
        mutex_lock(&adev->srbm_mutex);
-       soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0);
+       soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
 
        /* disable the queue if it's active */
        if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
 
        soc21_grbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
-
-       adev->mes.ring.sched.ready = false;
 }
 
 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
 
 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
 {
-       if (adev->mes.ring.sched.ready)
-               mes_v11_0_kiq_dequeue_sched(adev);
+       if (adev->mes.ring.sched.ready) {
+               mes_v11_0_kiq_dequeue(&adev->mes.ring);
+               adev->mes.ring.sched.ready = false;
+       }
+
+       if (amdgpu_sriov_vf(adev)) {
+               mes_v11_0_kiq_dequeue(&adev->gfx.kiq.ring);
+       }
 
        if (!amdgpu_sriov_vf(adev))
                mes_v11_0_enable(adev, false);