*/
#include <ppcboot.h>
-#include "L1.h"
#include <asm/processor.h>
-#include <i2c.h>
+#include <405gp_i2c.h>
#include <command.h>
#include <cmd_nvedit.h>
#include <cmd_bootm.h>
#include <rtc.h>
#include <net.h>
+#include <malloc.h>
-#define FACTORY_SETTINGS 0xFFFC0000
+#define L1_MEMSIZE (32*1024*1024)
+// the std. DHCP stufff
+#define DHCP_ROUTER 3
+#define DHCP_NETMASK 1
#define DHCP_BOOTFILE 67
#define DHCP_ROOTPATH 17
-#define DHCP_L1_FIRMWARE 220
-#define DHCP_L1_KERNEL 221
-#define DHCP_L1_ROOTFS 222
+#define DHCP_HOSTNAME 12
-#define XTFTP 0x100000 /* TFTP things to this addr for staging */
-#define TFTP_NAMELEN 128
+/* some extras used by CRAY
+ *
+ * on the server this looks like:
+ *
+ * option L1-initrd-image code 224 = string;
+ * option L1-initrd-image "/opt/craysv2/craymcu/l1/flash/initrd.image"
+ */
+#define DHCP_L1_INITRD 224
+
+/* new, [better?] way via official vendor-extensions, defining an option
+ * space.
+ * on the server this looks like:
+ *
+ * option space PPCBOOT;
+ * option PPCBOOT.initrd code 3 = string;
+ * option PPCBOOT.bootcmd code 4 = string;
+ * option PPCBOOT.bootflags code 5 = string;
+ * option PPCBOOT.rootdev code 6 = string;
+ */
+#define DHCP_VENDOR_SPECX 43
+#define DHCP_VX_INITRD 3
+#define DHCP_VX_BOOTCMD 4
+#define DHCP_VX_BOOTFLAGS 5
+#define DHCP_VX_ROOTDEV 6
/* Things DHCP server can tellme about. If there's no flash address, then
* they dont participate in 'update' to flash, and we force their values
- * back to '0' every boot to be sure to get them fresh from DHCP
+ * back to '0' every boot to be sure to get them fresh from DHCP. Yes, I
+ * know this is a pain...
+ *
+ * If I get no bootfile, boot from flash. If rootpath, use that. If no
+ * rootpath use initrd in flash.
*/
typedef struct dhcp_item_s {
u8 dhcp_option;
- char tftpname[TFTP_NAMELEN];
- char envname[16];
- u32 new_version;
- u32 flashaddr;
- u32 flashlen;
+ u8 dhcp_vendor_option;
+ char *dhcpvalue;
+ char *envname;
} dhcp_item_t;
static dhcp_item_t Things[] = {
- {DHCP_BOOTFILE, "", "bootfile", 0, 0, 0},
- {DHCP_ROOTPATH, "", "rootpath", 0, 0, 0},
- {DHCP_L1_FIRMWARE, "", "L1-firmware", 0, 0xFFFE0000, 0x020000},
- {DHCP_L1_KERNEL, "", "L1-kernel", 0, 0xFFF00000, 0x0C0000},
- {DHCP_L1_ROOTFS, "", "L1-rootfs", 0, 0xFFC00000, 0x300000}
+ {DHCP_ROUTER, 0, NULL, "gateway"},
+ {DHCP_NETMASK, 0, NULL, "netmask"},
+ {DHCP_BOOTFILE, 0, NULL, "bootfile"},
+ {DHCP_ROOTPATH, 0, NULL, "rootpath"},
+ {DHCP_HOSTNAME, 0, NULL, "hostname"},
+ {DHCP_L1_INITRD,0, NULL, "initrd"},
+// and the other way..
+ {DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"},
+ {DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"},
+ {DHCP_VENDOR_SPECX, DHCP_VX_BOOTFLAGS, NULL, NULL},
+ {DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL},
};
#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t)))
-static char buf[128];
-
-extern flash_info_t flash_info[]; /* info for FLASH chips */
-extern char BootFile[]; /* TFTP filename in net/net.c */
-extern ulong NetBootFileXferSize;
+static void init_ecc_sdram (void);
+/* ------------------------------------------------------------------------- */
int board_pre_init (void)
{
- /*-------------------------------------------------------------------------+
- | Interrupt controller setup for the Walnut board.
- | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
- | IRQ 16 405GP internally generated; active low; level sensitive
- | IRQ 17-24 RESERVED
- | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
- | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
- | IRQ 27 (EXT IRQ 2) Not Used
- | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
- | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
- | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
- | Note for Walnut board:
- | An interrupt taken for the FPGA (IRQ 25) indicates that either
- | the Mouse, Keyboard, IRDA, or External Expansion caused the
- | interrupt. The FPGA must be read to determine which device
- | caused the interrupt. The default setting of the FPGA clears
- |
- +-------------------------------------------------------------------------*/
-
+ init_ecc_sdram();
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical*/
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
-
return 0;
}
-
/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-
int checkboard (void)
{
-#if 0
- unsigned char *s = getenv("serial#");
- unsigned char *e;
-
- if (!s || strncmp(s, "CRAY_L1", 7))
- {
- printf ("### No HW ID - assuming CRAY_L1\n");
- }
- else
- {
- for (e=s; *e; ++e) {
- if (*e == ' ')
- break;
- }
-
- for ( ; s<e; ++s) {
- putc (*s);
- }
- }
-
- putc ('\n');
-#else
-#endif
return (0);
}
-
+/* ------------------------------------------------------------------------- */
void misc_init_r(bd_t *bd)
{
-unsigned char *s, *e, needsave=0;
+unsigned char *s, *e;
image_header_t *hdr;
time_t timestamp;
struct rtc_time tm;
-u8 thing;
hdr = (image_header_t *)(CFG_MONITOR_BASE - sizeof(image_header_t));
timestamp = (time_t)hdr->ih_time;
tm.tm_year, tm.tm_mon, tm.tm_mday,
tm.tm_hour, tm.tm_min, tm.tm_sec);
- if ((s = getenv("ethaddr")) == NULL)
+#define FACTORY_SETTINGS 0xFFFC0000
+ if ((s = getenv("ethaddr")) == NULL)
{
- printf ("No ENVIRONMENT:");
e = (unsigned char *)(FACTORY_SETTINGS);
- if (*e != '0')
+ if (*(e+0) != '0'
+ || *(e+1) != '0'
+ || *(e+2) != ':'
+ || *(e+3) != '4'
+ || *(e+4) != '0'
+ || *(e+17) != '\0' )
{
printf ("No valid MAC address in flash location 0x3C0000!\n");
}
{
printf ("Factory MAC: %s\n",e);
setenv ("ethaddr", e);
- // Serial# will later be sucked out of i2c
- // setenv ("serial#", "CRAY_L1");
- setenv ("dhcp_client_id", "crayL1");
- needsave++;
}
}
-// Also establish the baseline values for firmware,kernel,rootfs
- for ( thing=0; thing < N_THINGS; thing++)
- {
-// If the env setting doesn't yet exist, or for things that are NOT associated
-// with save-regions in firmware (i.e. only believe fresh DHCP values) we
-// set zero baselines.
- if (!Things[thing].flashaddr || (getenv(Things[thing].envname) == NULL))
- {
- setenv (Things[thing].envname,"");
- needsave++;
- }
- }
-
return;
}
-/*
- * ..in process...
- */
-/* ------------------------------------------------------------------------- */
-
-
-int do_crayL1(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
-{
-unsigned long addr, valu,old;
-u8 thing,need_save=0,only, *ptr;
-
-
- if (strcmp(argv[1], "update") == 0) // TFTP down updates.
- {
- only = 0xff;
- if ( argc > 2 )
- {
- for ( thing=0; thing < N_THINGS; thing++)
- {
- if (strcmp(argv[2], Things[thing].envname) == 0)
- {
- only = thing;
- break;
- }
- }
- if ( only == 0xff )
- {
- printf ("update one of: [ ");
- for ( thing=0; thing < N_THINGS; thing++)
- printf ("%s ",Things[thing].envname);
- printf ("]\n");
- return 1;
- }
- else
- printf ("Update %s\n",Things[only].envname);
- }
-
- for ( thing=0; thing < N_THINGS; thing++)
- {
- if (((only != 0xff) && (thing != only)) || !Things[thing].flashaddr)
- continue;
- printf ("check Update: %s..",Things[thing].envname);
- if ( strlen (Things[thing].tftpname))
- {
- old = simple_strtoul(getenv(Things[thing].envname),NULL,10);
- if ( Things[thing].new_version <= old )
- {
- printf ("..already up to date\n");
- continue;
- }
- printf ("needs updating, will TFTP <%s>\n",
- Things[thing].tftpname);
-
- load_addr = XTFTP;
- strcpy (BootFile,Things[thing].tftpname);
- if (NetLoop(bd, TFTP) == 0)
- printf ("fail to TFTP %s\n",Things[thing].tftpname);
- else
- {
- valu = NetBootFileXferSize & 0xffff0000;
- if (NetBootFileXferSize & 0xffff)
- valu += 0x10000;
-
- printf ("erasing flash regions: %x thru %lx\n",
- Things[thing].flashaddr,
- Things[thing].flashaddr + valu - 1);
-
- flash_sect_erase( Things[thing].flashaddr,
- Things[thing].flashaddr + valu - 1);
- printf ("updating flash: %lx bytes from %x to %x\n",
- valu, XTFTP, Things[thing].flashaddr);
- flash_write ((uchar *)XTFTP, Things[thing].flashaddr, valu);
-
- printf ("Updating environmet setting..\n");
- memset (Things[thing].tftpname,0,TFTP_NAMELEN);
- sprintf( buf,"%d",Things[thing].new_version);
- setenv (Things[thing].envname,buf);
- need_save = 1;
- }
- }
- else
- printf ("No TFTP update file DHCP-provided for %s\n",
- Things[thing].envname);
- }
- if (need_save)
- do_saveenv (NULL,NULL,0,0,NULL);
- return 0;
- }
-
- if (strcmp(argv[1], "boot") == 0) // boot ourselves up.
- {
-// Some process has happened; probably DHCP, and things have been updated.
-// I normally want to boot from image in flash, using rootfs in flash; that
-// is the contents of the 'ramboot' environment variable. If server has
-// given me a bootfile and rootpath, then we will assume that we are to boot
-// that way, with the 'nfsboot' environment string. Regardless, we ALWAYS
-// set up the ip= boot argument, since kernel lacks DHCP support still.
-
- if ((ptr = getenv ("bootfile")) && strlen(ptr))
- {
- load_addr = XTFTP;
- strcpy (BootFile,ptr);
- if (NetLoop(bd, TFTP) == 0)
- printf ("fail to TFTP boot image <%s>; revert to flash.\n",ptr);
- }
- else
- load_addr = 0xfff00000; /* flash kernel address */
-
- if ((ptr = getenv ("rootpath")) && strlen(ptr))
- run_command ("setenv bootargs "
- "root=/dev/nfs nfsroot=$(serverip):$(rootpath) "
- " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off"
- " ro devfs=mount",bd,0);
- else
- run_command ("setenv bootargs "
- "root=/dev/mtdblock/0 "
- " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off"
- " ro devfs=mount",bd,0);
-
- addr = load_addr;
- do_bootm (cmdtp, bd, 0, 1, NULL);
- return 0;
- }
- if (strcmp(argv[1], "regs") == 0) // Dump DCRs
- {
- printf("cray regs command..UNIMPLEMENTED.\n");
- return 1;
- }
- if (strcmp(argv[1], "mfdcr") == 0) // read a DCR from argv[2] (HEX!)
- {
- addr = simple_strtoul(argv[2], NULL, 16);
- printf("cray mfcdr command: read from DCR 0x%lx UNIMPLEMENTED.\n",addr);
- return 1;
- }
- if (strcmp(argv[1], "mtdcr") == 0) // write a DCR from argv[2] (HEX!)
- {
- addr = simple_strtoul(argv[2], NULL, 16);
- valu = simple_strtoul(argv[3], NULL, 16);
- printf("cray mtcdr command: write 0x%lx to DCR 0x%lx UNIMPLEMENTED\n",
- valu, addr);
- return 1;
- }
-
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
-}
-
-
-
-/* ------------------------------------------------------------------------- */
-
-/* ------------------------------------------------------------------------- */
-/*
- initdram(int board_type) does NOT! read the EEPROM on IIc, but instead
- returns hardwire 32M.
-*/
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
- return (32*1024*1024);
+ return (L1_MEMSIZE);
}
/* ------------------------------------------------------------------------- */
void rtc_set (struct rtc_time *tmp) {return;}
void rtc_reset (void) {return;}
+/* ------------------------------------------------------------------------- */
+/* Do sdram bank init in C so I can read it..
+ */
+static void init_ecc_sdram (void)
+{
+ unsigned long tmp, *p;
+
+ /* write SDRAM bank 0 register */
+ mtdcr(memcfga,mem_mb0cf);
+ mtdcr(memcfgd, 0x00062001);
+
+// Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
+// To set the appropriate timings, we need to know the SDRAM speed.
+// We can use the PLB speed since the SDRAM speed is the same as
+// the PLB speed. The PLB speed is the FBK divider times the
+// 405GP reference clock, which on the L1 is 25Mhz.
+// Thus, if FBK div is 2, SDRAM is 50Mhz; if FBK div is 3, SDRAM is
+// 150Mhz; if FBK is 3, SDRAM is 150Mhz.
+
+ // divisor = ((mfdcr(strap)>> 28) & 0x3);
+
+/* write SDRAM timing for 100Mhz. */
+ mtdcr(memcfga,mem_sdtr1);
+ mtdcr(memcfgd,0x0086400D);
+
+/* write SDRAM refresh interval register */
+ mtdcr(memcfga,mem_rtr);
+ mtdcr(memcfgd,0x05F00000);
+ udelay(200);
+
+/* sdram controller.*/
+ mtdcr(memcfga,mem_mcopt1);
+ mtdcr(memcfgd, 0x90800000);
+ udelay(200);
+
+/* disable ECC on all banks */
+ mtdcr(memcfga,mem_ecccf);
+ tmp=mfdcr(memcfgd);
+ tmp&=0xff0fffff;
+ mtdcr(memcfga,mem_ecccf);
+ mtdcr(memcfgd,tmp);
+
+/* set up SDRAM Controller with ECC enabled */
+ mtdcr(memcfga,mem_mcopt1);
+ tmp = (mfdcr(memcfgd) & ~0xFFE00000) | 0x90800000;
+ mtdcr(memcfga,mem_mcopt1);
+ mtdcr(memcfgd,tmp);
+ udelay(600);
+
+/* fill all the memory */
+ for (p=(unsigned long)0;((unsigned long)p<L1_MEMSIZE); *p++=0L)
+ ;
+ udelay(400);
+ mtdcr(memcfga,mem_ecccf);
+ tmp=mfdcr(memcfgd);
+
+/* enable ECC on bank 0 */
+ tmp|=0x00800000;
+ mtdcr(memcfgd,tmp);
+ udelay(400);
+
+ return ;
+}
/* ------------------------------------------------------------------------- */
+static u8 *
+dhcp_env_update (u8 thing,u8 *pop)
+{
+u8 i, oplen;
+ oplen = *(pop + 1);
+ if ((Things[thing].dhcpvalue = malloc(oplen)) == NULL)
+ {
+ printf ("Whoops! failed to malloc space for DHCP thing %s\n",
+ Things[thing].envname);
+ return NULL;
+ }
+ for(i=0;(i<oplen);i++)
+ if ((*(Things[thing].dhcpvalue+i) = *(pop+2+i)) == ' ')
+ break;
+ *(Things[thing].dhcpvalue+i) = '\0';
+
+/* set env. */
+ if (Things[thing].envname)
+ setenv (Things[thing].envname, Things[thing].dhcpvalue);
+ return (Things[thing].dhcpvalue);
+}
+
+/* ------------------------------------------------------------------------- */
u8 *dhcp_vendorex_prep(u8 *e)
{
u8 thing;
-char *ptr;
-/* my DHCP_CLIENT_IDENTIFIER = 61 */
- if ((ptr = getenv("dhcp_client_id")))
- {
- *e++ = 61;
- *e++ = strlen(ptr);
- while (*ptr)
- *e++ = *ptr++;
- }
+/* ask for the things I want. */
*e++ = 55; /* Parameter Request List */
*e++ = N_THINGS;
for ( thing=0; thing < N_THINGS; thing++)
}
/* ------------------------------------------------------------------------- */
-u8 *dhcp_vendorex_proc(u8 *popt)
+/* .. return NULL means it wasnt mine, non-null means I got it..*/
+u8 *dhcp_vendorex_proc(u8 *pop)
{
-u8 oplen,thing,i;
-
-/* have TFTP filenames and some version#. If no version# then version=0. */
- oplen = *(popt + 1);
+u8 oplen,*sub_op, sub_oplen,thing, *retval;
- for ( thing=0; thing < N_THINGS; thing++)
- {
- if (*popt == Things[thing].dhcp_option)
- {
- for(i=0;((i<TFTP_NAMELEN) && (i<oplen));i++)
- if ((Things[thing].tftpname[i] = *(popt+2+i)) == ' ')
- break;
- Things[thing].tftpname[i] = '\0';
- while (*(popt+2+i) == ' ') i++;
- Things[thing].new_version = simple_strtoul(popt+2+i,NULL,10);
- printf ("L1-DHCP: image for %s <%s> have#=%s need#=%d\n",
- Things[thing].envname,
- Things[thing].tftpname,
- getenv (Things[thing].envname),
- Things[thing].new_version);
- break;
- }
- }
- return ( thing >= N_THINGS ? NULL : popt);
+ retval = NULL;
+ oplen = *(pop + 1);
+// if pop is vender spec indicator, there are sub-options.
+ if (*pop == DHCP_VENDOR_SPECX)
+ {
+ for ( sub_op = pop+2;
+ oplen && (sub_oplen = *(sub_op + 1));
+ oplen -= sub_oplen, sub_op += (sub_oplen + 2))
+ for ( thing=0; thing < N_THINGS; thing++)
+ if (*sub_op == Things[thing].dhcp_vendor_option)
+ if (!(retval = dhcp_env_update (thing,sub_op)))
+ return NULL;
+ }
+ else for ( thing=0; thing < N_THINGS; thing++)
+ {
+ if (*pop == Things[thing].dhcp_option)
+ if (!(retval = dhcp_env_update (thing,pop)))
+ return NULL;
+ }
+ return ( thing >= N_THINGS ? NULL : pop);
}
#include <ppc4xx.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-#define FPGA_BRDC 0xF0300004
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
//-------------------------------------------------------------------
// Delay to ensure all accesses to ROM are complete before changing
- // bank 0 timings. 200usec should be enough.
+ // bank 0 timings. 200usec should be enough.
// 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
//-------------------------------------------------------------------
addis r3,0,0x0
//----------------------------------------------------------------------
- // Memory Bank 0 (Flash and SRAM) initialization
+ // Peripheral Bank 0 (Flash) initialization
//----------------------------------------------------------------------
+ // 0x7F8FFE80 slowest boot
addi r4,0,pb0ap
mtdcr ebccfga,r4
addis r4,0,0x9B01
ori r4,r4,0x8000 // BW=0x0( 8 bits)
mtdcr ebccfgd,r4
+ blr
+
//----------------------------------------------------------------------
- // Memory Bank 1 (NVRAM/RTC) initialization
- // CRAY:the L1 has NOT this bank; it is tied to SV2/IOCA/etc/ instead
+ // Peripheral Bank 1 (NVRAM/RTC) initialization
+ // CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead
// and we do DMA on it. The ConfigurationRegister part is threfore
// almost arbitrary, except that our linux driver needs to know the
// address, but it can query, it..
//-----------------------------------------------------------------------------
// Function: sdram_init
// Description: Configures SDRAM memory banks.
-// Auto Memory Configuration option reads the SDRAM EEPROM
-// via the IIC bus and then configures the SDRAM memory
-// banks appropriately. If Auto Memory Configuration is
-// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is
-// plugged, ie. the DIMM that shipped wih the Eval board.
+// NOTE: for CrayL1 we have ECC memory, so enable it.
+//....now done in C in L1.c:init_sdram for readability.
//-----------------------------------------------------------------------------
.globl sdram_init
sdram_init:
-
- mflr r31
-
-//-------------------------------------------------------------------
-// Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4)
-//-------------------------------------------------------------------
- addi r4,0,mem_mb0cf
- mtdcr memcfga,r4
- addis r4,0,0x0006
- ori r4,r4,0x2001
- mtdcr memcfgd,r4
-
-//-------------------------------------------------------------------
-// Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
-// To set the appropriate timings, we need to know the SDRAM speed.
-// We can use the PLB speed since the SDRAM speed is the same as
-// the PLB speed. The PLB speed is the FBK divider times the
-// 405GP reference clock, which on the Walnut board is 33Mhz.
-// Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is
-// 100Mhz; if FBK is 3, SDRAM is 133Mhz.
-// NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and
-// maybe 133Mhz.
-//-------------------------------------------------------------------
- mfdcr r5,strap // determine FBK divider
- // via STRAP reg to calc PLB speed.
- // SDRAM speed is the same as the PLB
- // speed.
- rlwinm r4,r5,4,0x3 // get FBK divide bits
-
-..chk_66:
- cmpi %cr0,0,r4,0x1
- bne ..chk_100
- addis r6,0,0x0085 // SDTR1 value for 66Mhz
- ori r6,r6,0x4005
- addis r7,0,0x03F8 // RTR value for 66Mhz
- b ..sdram_ok
-..chk_100:
- cmpi %cr0,0,r4,0x2
- bne ..chk_133
- addis r6,0,0x0086 // SDTR1 value for 100Mhz
- ori r6,r6,0x400D
- addis r7,0,0x05F0 // RTR value for 100Mhz
- b ..sdram_ok
-..chk_133:
- addis r6,0,0x0107 // SDTR1 value for 133Mhz
- ori r6,r6,0x4015
- addis r7,0,0x07F0 // RTR value for 133Mhz
-
-..sdram_ok:
- //-------------------------------------------------------------------
- // Set SDTR1
- //-------------------------------------------------------------------
- addi r4,0,mem_sdtr1
- mtdcr memcfga,r4
- mtdcr memcfgd,r6
-
- //-------------------------------------------------------------------
- // Set RTR
- //-------------------------------------------------------------------
- addi r4,0,mem_rtr
- mtdcr memcfga,r4
- mtdcr memcfgd,r7
-
- //-------------------------------------------------------------------
- // Delay to ensure 200usec have elapsed since reset. Assume worst
- // case that the core is running 200Mhz:
- // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- //-------------------------------------------------------------------
- addis r3,0,0x0000
- ori r3,r3,0xA000 // ensure 200usec have passed since reset
- mtctr r3
-..spinlp2:
- bdnz ..spinlp2 // spin loop
-
- //-------------------------------------------------------------------
- // Set memory controller options reg, MCOPT1.
- // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
- // read/prefetch.
- //-------------------------------------------------------------------
- addi r4,0,mem_mcopt1
- mtdcr memcfga,r4
- addis r4,0,0x8080 // set DC_EN=1
- ori r4,r4,0x0000
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Delay to ensure 10msec have elapsed since reset. This is
- // required for the MPC952 to stabalize. Assume worst
- // case that the core is running 200Mhz:
- // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles
- // This delay should occur before accessing SDRAM.
- //-------------------------------------------------------------------
- addis r3,0,0x001E
- ori r3,r3,0x8480 // ensure 10msec have passed since reset
- mtctr r3
-..spinlp3:
- bdnz ..spinlp3 // spin loop
-
- mtlr r31 // restore lr
- blr
+ blr
* (easy to change)
*/
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC405 family */
-#define CONFIG_BOARD_PRE_INIT 1 /* setup for 405gp */
-#define CONFIG_SYS_CLK_FREQ 25000000 /* .. frequency in L1 */
-
-#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#undef CFG_ENV_IS_IN_NVRAM /* NO!use NVRAM for environment vars */
-#define CONFIG_MISC_INIT_R 1 /* call a misc_init when basic setup done, */
- /* in our case, make sure we have ethaddr */
-
-
-
-/* Default environment stuff */
+#define CONFIG_405GP 1 /* This is a PPC405 CPU */
+#define CONFIG_4xx 1 /* ...member of PPC405 family */
+#define CONFIG_SYS_CLK_FREQ 25000000
#define CONFIG_BAUDRATE 9600
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CFG_AUTOLOAD "no"
-
-#define CONFIG_BOOTCOMMAND "setenv autostart no; "\
- "setenv autoload no; "\
- "dhcp; "\
- "L1cmd update; "\
- "L1cmd boot"
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */
+#define CONFIG_BOARD_PRE_INIT 1 /* setup for 405gp */
+#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */
+
+/* set PRAM to keep ppcboot out, mem= to keep linux out, and initrd_hi to
+ * keep possible initrd ramdisk decompression out. This is in k (1024 bytes)
+ #define CONFIG_PRAM 16
+ */
+#define CONFIG_LOADADDR 0x100000
+#undef CONFIG_BOOTARGS
+
+/* the logic is that booting is driven by what env vars get set from DHCP.
+ * Normal DHCP sets things like serverip, rootpath, etc.
+ * if printenv
+ */
+#define CFG_AUTOLOAD "yes"
+#define CONFIG_BOOTCOMMAND "dhcp;"\
+ "setenv bootargs devfs=mount;"\
+ "setenv bootargs ip=$ipaddr:$serverip:$gatewayip:$netmask:::off $bootargs;"\
+ "if printenv initrd;"\
+ "then;" \
+ "setenv initrd_hi $mem;"\
+ "tftp 1000000 $initrd;"\
+ "setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs;"\
+ "bootm 100000 1000000;"\
+ "else;"\
+ "setenv bootargs root=/dev/nfs ro nfsroot=$serverip:$rootpath $bootargs;"\
+ "bootm 100000;"\
+ "fi;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS ""
+
+/*
+ * ..during experiments..
+ #define CONFIG_SERVERIP 10.0.0.1
+ #define CONFIG_ETHADDR 00:40:a6:80:14:5
+ */
+#define CONFIG_HARD_I2C 1 /* hardware support for i2c */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_IDENT_STRING "Cray L1"
+#define CONFIG_ENV_OVERWRITE 1
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HUSH_PARSER 1
+#define CFG_PROMPT_HUSH_PS2 "> "
#define CONFIG_COMMANDS (\
CFG_CMD_CONSOLE|\
CFG_CMD_ASKENV|\
CFG_CMD_ECHO|\
+ CFG_CMD_IMMAP|\
CFG_CMD_REGINFO|\
CFG_CMD_DHCP|\
CFG_CMD_DATE|\
CFG_CMD_RUN|\
- CFG_CMD_BSP)
-
-#if LATER_ON
- CFG_CMD_RUN
- CFG_CMD_CACHE
- CFG_CMD_EEPROM
- CFG_CMD_I2C
- CFG_CMD_IMMAP
-#endif
-
-
+ CFG_CMD_I2C|\
+ CFG_CMD_EEPROM|\
+ CFG_CMD_SETGETDCR)
/*
- * optional BOOTP fields
- */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_VENDOREX\
- |CONFIG_BOOTP_SUBNETMASK\
- |CONFIG_BOOTP_GATEWAY\
- |CONFIG_BOOTP_DNS\
- |CONFIG_BOOTP_HOSTNAME\
- |CONFIG_BOOTP_BOOTFILESIZE\
- |CONFIG_BOOTP_BOOTPATH)
+ * optional BOOTP / DHCP fields
+ */
+#define CONFIG_BOOTP_MASK (\
+ CONFIG_BOOTP_VENDOREX|\
+ CONFIG_BOOTP_SUBNETMASK|\
+ CONFIG_BOOTP_GATEWAY|\
+ CONFIG_BOOTP_DNS|\
+ CONFIG_BOOTP_HOSTNAME|\
+ CONFIG_BOOTP_BOOTFILESIZE|\
+ CONFIG_BOOTP_BOOTPATH)
+
+/*
+ * bauds. Just to make it compile; in our case, I read the base_baud
+ * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
+ * drives the system clock.
+ */
+#define CFG_BASE_BAUD 403225
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
-#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CFG_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_LOAD_ADDR 0x100000/* where to load what we get from TFTP */
+#define CFG_TFTP_LOADADDR CFG_LOAD_ADDR
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_PCI /* DO NOT include pci support */
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* no reset for ide supported */
-
-#undef CFG_KEY_REG_BASE_ADDR /* NO! peripherals... */
-#undef CFG_IR_REG_BASE_ADDR
-#undef CFG_FPGA_REG_BASE_ADDR
-
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFFC00000
-#define CFG_MONITOR_BASE 0xFFFE0040
+#define CFG_MONITOR_BASE TEXT_BASE
+
+#ifndef CFG_HUSH_PARSER
+#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */
+#define CFG_ENV_OFFSET 0x3D0000
+#else
+#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
+#define CFG_ENV_OFFSET 0x3FE000
+#endif
-#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
/*
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */
-#define CFG_ENV_OFFSET 0x003D0000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
/* Memory tests: PPCBOOT relocates itself to the top of Ram, so its at
* 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
*/
-#if 0
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-#else
-
-
-#define CFG_SDRAM_SIZE 32 /* megs of ram */
-#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
- /* the exception vector table */
- /* to the end of the DRAM */
- /* less monitor and malloc area */
-#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
-#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
+#define CFG_SDRAM_SIZE 32 /* megs of ram */
+#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
+ /* the exception vector table */
+ /* to the end of the DRAM */
+ /* less monitor and malloc area */
+#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
+#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
+ CFG_MALLOC_LEN \
+ CFG_ENV_SECT_SIZE \
+ CFG_STACK_USAGE )
-#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
- - CFG_MEM_END_USAGE )
-#endif
+#define CFG_MEMTEST_END (CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE)
/* END ENVIRONNEMENT FLASH */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#undef CFG_NVRAM_BASE_ADDR
/*-----------------------------------------------------------------------
- * Cache Configuration
+ * Cache Configuration. Only used to ..?? clear it, I guess..
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
+#define CFG_DCACHE_SIZE 16384
+#define CFG_CACHELINE_SIZE 32
/*
* Init Memory Controller:
*/
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
+ * Definitions for initial stack pointer and data area (in OnChipMem )
*/
-#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
-#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */
-#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#if 0
+#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#else
+#define CFG_TEMP_STACK_OCM 1
+#define CFG_OCM_DATA_ADDR 0xF0000000
+#define CFG_OCM_DATA_SIZE 0x1000
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
+#endif
+
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
/*-----------------------------------------------------------------------
* Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- * DBU: we may yet use these someday..
*/
#define EEPROM_WRITE_ADDRESS 0xA0
#define EEPROM_READ_ADDRESS 0xA1
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
#endif /* __CONFIG_H */
projects / users / rw / ppcboot.git / commitdiff