drm/i915: pass dev_priv explicitly to DSPSURF

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPSURF register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/fc2d7753aa6e8e25303a111bf4b120da6ce8c458.1716469091.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 42175cb74d5da3bde3b6546bdb3e8fbec9752147..7adaf8cbd9452776551f6c331a97676aa68b3bc4 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -499,7 +499,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
        intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
 
        if (DISPLAY_VER(dev_priv) >= 4)
-               intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
+               intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane),
                                  intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
        else
                intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane),
@@ -542,7 +542,7 @@ static void i9xx_plane_disable_arm(struct intel_plane *plane,
        intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
 
        if (DISPLAY_VER(dev_priv) >= 4)
-               intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
+               intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), 0);
        else
                intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 0);
 }
@@ -563,7 +563,7 @@ g4x_primary_async_flip(struct intel_plane *plane,
 
        intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
 
-       intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
+       intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane),
                          intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
 }
 
@@ -1034,7 +1034,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
        if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
                offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
-               base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
+               base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK;
        } else if (DISPLAY_VER(dev_priv) >= 4) {
                if (plane_config->tiling)
                        offset = intel_de_read(dev_priv,
@@ -1042,7 +1042,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
                else
                        offset = intel_de_read(dev_priv,
                                               DSPLINOFF(dev_priv, i9xx_plane));
-               base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
+               base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK;
        } else {
                offset = 0;
                base = intel_de_read(dev_priv, DSPADDR(dev_priv, i9xx_plane));
@@ -1094,7 +1094,7 @@ bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,
                return false;
 
        if (DISPLAY_VER(dev_priv) >= 4)
-               intel_de_write(dev_priv, DSPSURF(i9xx_plane), base);
+               intel_de_write(dev_priv, DSPSURF(dev_priv, i9xx_plane), base);
        else
                intel_de_write(dev_priv, DSPADDR(dev_priv, i9xx_plane), base);
 

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 5a1f45eceed4f774c3c5d9da5b840846e8a70c6a..2771f2a7645b228c2a4a9a79abc4206b0aa952ff 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -67,7 +67,7 @@
 #define   DISP_WIDTH(w)                        REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
 
 #define _DSPASURF                              0x7019C /* i965+ */
-#define DSPSURF(plane)                         _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
+#define DSPSURF(dev_priv, plane)               _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
 #define   DISP_ADDR_MASK               REG_GENMASK(31, 12)
 
 #define _DSPATILEOFF                           0x701A4 /* i965+ */

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index f46e01cad05372cc218f04f2015bc84968a129b1..e9189a864f696bc5ffa718ee1ffa53f2589b40a6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -364,8 +364,8 @@ static void i965_fbc_nuke(struct intel_fbc *fbc)
        enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
        struct drm_i915_private *dev_priv = fbc->i915;
 
-       intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
-                         intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
+       intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane),
+                         intel_de_read_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane)));
 }
 
 static const struct intel_fbc_funcs i965_fbc_funcs = {

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 7072d14d86cf7357b8bcc3e6a466d2a935b352cc..9cdb53015d1644b03145ac84294461f02154b47d 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1317,7 +1317,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
        if (info->plane == PLANE_A) {
                info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
                info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
-               info->surf_reg = DSPSURF(info->pipe);
+               info->surf_reg = DSPSURF(dev_priv, info->pipe);
        } else if (info->plane == PLANE_B) {
                info->ctrl_reg = SPRCTL(info->pipe);
                info->stride_reg = SPRSTRIDE(info->pipe);
@@ -1383,7 +1383,7 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s,
 
        info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
        info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
-       info->surf_reg = DSPSURF(info->pipe);
+       info->surf_reg = DSPSURF(dev_priv, info->pipe);
 
        return 0;
 }

diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index cf1cff3d1c4f0d2ba856a7cfac2a063b9130d82b..6c3a0f160bea7e4f8b0e6453e9fba177074bb6f6 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -251,7 +251,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
 
        plane->hw_format = fmt;
 
-       plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;
+       plane->base = vgpu_vreg_t(vgpu, DSPSURF(dev_priv, pipe)) & I915_GTT_PAGE_MASK;
        if (!vgpu_gmadr_is_valid(vgpu, plane->base))
                return  -EINVAL;
 

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 56fb606b4a3dbaed15fc31087f76efd629ddf679..abcb8f0825e054c7b491e4c647c82a71a5e1a713 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1008,7 +1008,7 @@ static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
 }
 
 #define DSPSURF_TO_PIPE(offset) \
-       calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
+       calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(dev_priv, PIPE_C))
 
 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
                void *p_data, unsigned int bytes)
@@ -2276,13 +2276,13 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
        MMIO_DH(TRANSCONF(TRANSCODER_B), D_ALL, NULL, pipeconf_mmio_write);
        MMIO_DH(TRANSCONF(TRANSCODER_C), D_ALL, NULL, pipeconf_mmio_write);
        MMIO_DH(TRANSCONF(TRANSCODER_EDP), D_ALL, NULL, pipeconf_mmio_write);
-       MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
+       MMIO_DH(DSPSURF(dev_priv, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
        MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
                reg50080_mmio_write);
-       MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
+       MMIO_DH(DSPSURF(dev_priv, PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
        MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
                reg50080_mmio_write);
-       MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
+       MMIO_DH(DSPSURF(dev_priv, PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
        MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
                reg50080_mmio_write);
        MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);

diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 59d50195c144d6baac379253157485fd96a58a90..db4fbb6a803d18188f26b3d0da23e49f7425587a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -141,8 +141,10 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
                intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(dev_priv, pipe),
                                 0, DISP_TRICKLE_FEED_DISABLE);
 
-               intel_uncore_rmw(&dev_priv->uncore, DSPSURF(pipe), 0, 0);
-               intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe));
+               intel_uncore_rmw(&dev_priv->uncore, DSPSURF(dev_priv, pipe),
+                                0, 0);
+               intel_uncore_posting_read(&dev_priv->uncore,
+                                         DSPSURF(dev_priv, pipe));
        }
 }
 

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index e047928c3ea0c327e62ad991315a5b260ca9bf66..a8be80bde2e7927c2063ef55ff74e168ac153460 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -170,7 +170,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(DSPSTRIDE(dev_priv, PIPE_A));
        MMIO_D(DSPPOS(dev_priv, PIPE_A));
        MMIO_D(DSPSIZE(dev_priv, PIPE_A));
-       MMIO_D(DSPSURF(PIPE_A));
+       MMIO_D(DSPSURF(dev_priv, PIPE_A));
        MMIO_D(DSPOFFSET(PIPE_A));
        MMIO_D(DSPSURFLIVE(PIPE_A));
        MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
@@ -179,7 +179,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(DSPSTRIDE(dev_priv, PIPE_B));
        MMIO_D(DSPPOS(dev_priv, PIPE_B));
        MMIO_D(DSPSIZE(dev_priv, PIPE_B));
-       MMIO_D(DSPSURF(PIPE_B));
+       MMIO_D(DSPSURF(dev_priv, PIPE_B));
        MMIO_D(DSPOFFSET(PIPE_B));
        MMIO_D(DSPSURFLIVE(PIPE_B));
        MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY));
@@ -188,7 +188,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(DSPSTRIDE(dev_priv, PIPE_C));
        MMIO_D(DSPPOS(dev_priv, PIPE_C));
        MMIO_D(DSPSIZE(dev_priv, PIPE_C));
-       MMIO_D(DSPSURF(PIPE_C));
+       MMIO_D(DSPSURF(dev_priv, PIPE_C));
        MMIO_D(DSPOFFSET(PIPE_C));
        MMIO_D(DSPSURFLIVE(PIPE_C));
        MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY));