CLK_S3,
        CLK_SDSRC,
        CLK_SSPSRC,
+       CLK_RPCSRC,
        CLK_RINT,
 
        /* Module Clocks */
        DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
        DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
        DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
+       DEF_BASE(".rpcsrc",     CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+       DEF_BASE("rpc",         R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
+                CLK_RPCSRC),
+       DEF_BASE("rpcd2",       R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+                R8A7795_CLK_RPC),
 
        DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
 
        DEF_MOD("can-fd",                914,   R8A7795_CLK_S3D2),
        DEF_MOD("can-if1",               915,   R8A7795_CLK_S3D4),
        DEF_MOD("can-if0",               916,   R8A7795_CLK_S3D4),
+       DEF_MOD("rpc-if",                917,   R8A7795_CLK_RPCD2),
        DEF_MOD("i2c6",                  918,   R8A7795_CLK_S0D6),
        DEF_MOD("i2c5",                  919,   R8A7795_CLK_S0D6),
        DEF_MOD("i2c-dvfs",              926,   R8A7795_CLK_CP),