wifi: rtw89: pci: add to do PCI auto calibration

8852be needs this with n times calibration to correct hardware clock.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220927062611.30484-6-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c
index 957f4e550a7efa7a876c27d27eadb8c78bf1e49b..b52edf2cf7434db1016640bc36437c2c286ae999 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci.c
+++ b/drivers/net/wireless/realtek/rtw89/pci.c
@@ -1874,6 +1874,18 @@ __get_target(struct rtw89_dev *rtwdev, u16 *target, enum rtw89_pcie_phy phy_rate
        return 0;
 }
 
+static int rtw89_pci_autok_x(struct rtw89_dev *rtwdev)
+{
+       int ret;
+
+       if (rtwdev->chip->chip_id != RTL8852B)
+               return 0;
+
+       ret = rtw89_write16_mdio_mask(rtwdev, RAC_REG_FLD_0, BAC_AUTOK_N_MASK,
+                                     PCIE_AUTOK_4, PCIE_PHY_GEN1);
+       return ret;
+}
+
 static int rtw89_pci_auto_refclk_cal(struct rtw89_dev *rtwdev, bool autook_en)
 {
        enum rtw89_pcie_phy phy_rate;
@@ -2452,6 +2464,12 @@ static int rtw89_pci_ops_mac_pre_init(struct rtw89_dev *rtwdev)
        rtw89_pci_hci_ldo(rtwdev);
        rtw89_pci_dphy_delay(rtwdev);
 
+       ret = rtw89_pci_autok_x(rtwdev);
+       if (ret) {
+               rtw89_err(rtwdev, "[ERR] pcie autok_x fail %d\n", ret);
+               return ret;
+       }
+
        ret = rtw89_pci_auto_refclk_cal(rtwdev, false);
        if (ret) {
                rtw89_err(rtwdev, "[ERR] pcie autok fail %d\n", ret);

diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h
index e49ffc9cf790303673a8654e7c5fcb6b7f2e40ea..179740607778a54a63c1c1cc3e9762e8a8e912cc 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci.h
+++ b/drivers/net/wireless/realtek/rtw89/pci.h
@@ -23,6 +23,9 @@
 #define PCIE_DPHY_DLY_25US             0x1
 #define RAC_ANA19                      0x19
 #define B_PCIE_BIT_RD_SEL              BIT(2)
+#define RAC_REG_FLD_0                  0x1D
+#define BAC_AUTOK_N_MASK               GENMASK(3, 2)
+#define PCIE_AUTOK_4                   0x3
 #define RAC_ANA1F                      0x1F
 #define RAC_ANA24                      0x24
 #define B_AX_DEGLITCH                  GENMASK(11, 8)